Shared hardware for multiply, divide, and square root exponent c

Details Shared hardware for multiply, divide, and square root exponent c Shared hardware for multiply, divide, and square root exponent c

1995-07-05

1997-04-08

Ngo, Chuong D.

Boots, shoes, and leggings

G06F 738

Patent

active

056194390

ABSTRACT:
The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending. A multiplexor select between the presently calculated exponents and the saved exponents calculated for a pending division or square root operation. If the instruction scheduler has flexibility in allowing out of order instruction completion, younger multiplication instructions can be dispatched and completed during the several machine cycles during which the division/square root mantissa computation.

REFERENCES:
patent: 4975868 (1990-12-01), Freerksen
patent: 5150320 (1992-09-01), Nakayama
patent: 5548545 (1996-08-01), Brashears et al.
Claude P. Lerouge, Pierre Girard, Joel S. Colardelle, "A Fast 16 Bit NMOS Parallel Multiplier", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 3, Jun. 1984 pp. 338-342.
Ramautar Sharma, Alexander D. Lopez, John A. Michejda, Steven J. Hillenius, John M. Andrews, Arnold J. Studwell, "A 6.75-ns 16.times.16-bit Multiplier in Single-Level-Metal CMOS Technology", IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989 pp. 922-926.
W.K. Luk, J.E. Vuillemin, "Recursive Implementation of Optimal Time VLSI Integer Multipliers", 1983 pp. 155-168.

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