Shared buffer memory architecture for asynchronous transfer mode

Details Shared buffer memory architecture for asynchronous transfer mode Shared buffer memory architecture for asynchronous transfer mode

1997-02-26

2000-06-27

Ngo, Ricky

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370412, 370423, 370429, 36523005, G11C 2900

Patent

active

060815280

ABSTRACT:
An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.

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