Shared bit line cross point memory array

Details Shared bit line cross point memory array Shared bit line cross point memory array

2001-09-26

2003-05-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Resistor

C438S238000, C438S386000

Reexamination Certificate

active

06569745

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to nonvolatile memory, and more particularly to a cross point memory structure.
Materials having a perovskite structure, among them colossal magnetoresistance (CMR) materials and high temperature superconductivity (HTSC) materials are materials that have electrical resistance characteristics that can be changed by external influences.
For instance, the properties of materials having perovskite structures, especially for CMR and HTSC materials, can be modified by applying one or more short electrical pulses to a thin film or bulk material. The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material. The pulse is of low enough energy so as not to destroy, or significantly damage, the material. Multiple pulses may be applied to the material to produce incremental changes in properties of the material. One of the properties that can be changed is the resistance of the material. The change may be at least partially reversible using pulses of opposite polarity from those used to induce the initial change.
Cross point memory arrays along with their accompanying read out circuits can use a significant amount of chip surface area. The reduction in chip size has a corresponding economic benefit.
SUMMARY OF THE INVENTION
Accordingly, a memory structure is provided, which reduces the area needed for a cross point array and accompanying read out circuits. By sharing each bit line with two sets of word lines, the area of each cross point can hold two bits instead of one, and the number of read out circuits is reduced since the number of bit lines per bit is reduced.
A shared bit line cross point memory array structure is provided, along with methods of manufacture and use. The memory structure comprises a bottom word line with a top word line overlying the bottom word line. A bit line is interposed between the bottom word line and the top word line such that a first cross point is formed between the bottom word line and the bit line and a second cross point is formed between the bit line and the top word line. A material having a property, for example resistance, that can be changed in response to an input voltage is provided at each cross point above and below the bit line.
Each bit can be programmed by applying a voltage signal between the bit line and the appropriate word line while leaving other word lines floating. Likewise, the bit can be read by applying a read voltage to the desired word line and reading the signal off of the bit line. A block erase can also be achieved by ground all word lines and applying an erase voltage signal to one, or more, bit lines.


REFERENCES:
patent: 5991188 (1999-11-01), Chung et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6204139 (2001-03-01), Liu et al.
US 2002/0075719, Yamada et al. Apr. 18, 2002.*
US 2002/0043680, Johnson et al., Jun. 18, 2002.*
Article entitled, “Electric-pulse-induced reversible resistance change effect in magnetoresistive films”, by S. Q. Liu et al., published in Applied Physics Letters, vol. 76, No. 19, May 8, 2000, pp 2749-2751.
Article entitled, “Reproducible Switching Effect in Thin Oxide Films for Memory Applications”, by A. Beck et al., published in Applied Physics Letters, vol. 77, No. 1, Jul. 3, 2000, pp. 139-141.

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