Shallow trench isolation with thin nitride as gate dielectric

Details Shallow trench isolation with thin nitride as gate dielectric Shallow trench isolation with thin nitride as gate dielectric

1997-12-05

1999-09-14

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257649, 257510, H01L 2951

Patent

active

059527072

ABSTRACT:
A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top layer comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

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patent: 5650654 (1997-07-01), Noble
patent: 5859466 (1999-01-01), Wada

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