Shallow trench isolation with self aligned PSG layer

Details Shallow trench isolation with self aligned PSG layer Shallow trench isolation with self aligned PSG layer

1995-06-01

1997-04-01

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

And gettering of substrate

438433, 438473, H01L 2176

Patent

active

056165137

ABSTRACT:
A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

REFERENCES:
patent: 4679308 (1987-07-01), Finn et al.
patent: 4740480 (1988-04-01), Ooka
patent: 5362669 (1994-11-01), Boyd et al.
S. M. Sze, "Physics of Semiconductor Devices" 2nd edition, John Wiley & Sons, 1981, pp. 372-396.

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