Shallow trench isolation using UV/O3 passivation prior to...

Details Shallow trench isolation using UV/O3 passivation prior to... Shallow trench isolation using UV/O3 passivation prior to...

1999-07-02

2001-03-27

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S769000, C438S770000, C438S219000

Reexamination Certificate

active

06207531

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of forming isolation for integrated circuits, and more specifically, to a method of forming a shallow trench isolation.
BACKGROUND OF THE INVENTION
In the formation of integrated circuits, the manufacture of isolation structures between semiconductor devices for insulating is crucial. In either ULSI or in VLSI, a tiny amount of leakage current can induce significant power dissipation for the entire circuit. Therefore, it is very important to form an effective isolation between semiconductor devices. In addition, with the trend towards higher density integration, effective isolation must be done in a smaller isolation space.
Presently, various isolation technologies have been proposed. These include: LOCOS (LOCal Oxidation of Silicon) and shallow trench isolation (STI) technologies. The most widely used method for forming isolation regions is the LOCOS structure. The LOCOS structure involves the formation of Field OXides (FOX) in the nonactive regions of the semiconductor substrate. In the other words, the FOX is created on the wafer that is not covered by a silicon nitride/silicon oxide composition layer. Unfortunately, the surface topography of the FOX cannot meet the stringent space demands of submicron devices. Additionally, as device geometry reaches submicron size, conventional LOCOS isolation has a further limitation. Notably, the bird's beak effect causes unacceptably large encroachment of the FOX into the device active regions.
Trench isolation is one of the newer approaches adopted and is used primarily for isolating devices in VLSI and ULSI. Trench isolation can be considered as a replacement for conventional LOCOS isolation. In the basic STI technology, a pad layer is first formed on the semiconductor wafer. The pad oxide layer may be formed by oxidizing a bare silicon wafer in a furnace to grow the pad oxide layer of about 100 to 250 angstroms thickness. The pad oxide layer is most typically formed from silicon dioxide.
Next, a furnace nitride layer of about 1500 to 2000 angstroms thickness is then deposited on the pad oxide layer. The silicon nitride layer is used as a stop layer and is formed on the pad oxide layer. A masking and etching step is then performed to form trenches about 0.4 to 0.5 &mgr;m in depth by anisotropically etched into the silicon wafer. Then, a CVD oxide is deposited onto the wafer and is subsequently planarized by CMP (chemical mechanical polishing) or etching back.
One drawback of conventional trench isolation is a relatively weak isolation due to the its oxide quality. As is well known in the art, the isolation formed by CVD is of poor quality. Therefore, an extra thermal process is often needed to density the oxide. Further, a thin liner oxide is frequently formed around the shallow trench when the conventional method is used. The thermal oxide process by definition requires a high temperature thermal cycle which depletes the thermal budget. Furthermore, the formation of the thermal oxide requires a relatively lengthy amount of time reducing throughput.
Thus, what is needed is an improved method for forming a shallow trench isolation without the need to form a thermal oxide layer.
SUMMARY OF THE INVENTION
A method of forming a shallow trench isolation on a substrate is disclosed. The method comprises: forming a pad oxide layer on said substrate; forming a dielectric layer on said pad oxide layer; forming at least one trench in said substrate; forming an oxide liner along the walls and bottom of said at least one trench, said oxide liner formed from a UV/O
3
process; and forming a CVD oxide layer for isolation atop said oxide liner and within said at least one trench.


REFERENCES:
patent: 6107159 (2000-08-01), Chuang
patent: 0 119 553 A1 (1984-09-01), None
patent: WO 96/28853 (1996-09-01), None
Ohkubo et al, High Quality Ultra-Thin (4nm) Gate Oxide by UV/03 Surface Pre-Treatment of Native Oxide, 1995 Symposium on VLSI Technology Digest of Technical Papers, p. 111-112.

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