Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-07-15
2003-09-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S692000
Reexamination Certificate
active
06613648
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor devices. More particularly, the present invention relates to a method and apparatus for preventing dishing that results from chemical mechanical polishing of shallow trench isolation structures.
2. Related Art
As semiconductor devices continue to be reduced in size, Complimentary Metal Oxide Semiconductor (CMOS) device fabrication processes have evolved that use shallow trench isolation structures for isolating device regions. These shallow trench isolation structures are typically formed by etching trenches within the semiconductor substrate in a pattern that achieves the desired isolation between adjoining device regions. The trenches are filled with dielectric material. A chemical mechanical polishing process is then performed to form a dielectric plug that fills the trench.
In conventional shallow trench isolation processes, the chemical mechanical polishing process results in “dishing” of the dielectric plug. More particularly, the chemical mechanical polishing process results in a top surface of the plug that is not planar. Instead, the top surface of the plug is recessed in a concave pattern with respect to the top surface of rest of the substrate.
Because the top surface of the semiconductor substrate is not planar as a result of dishing during chemical mechanical polishing, layers and structures that are subsequently formed over the semiconductor substrate are not uniform. This leads to manufacturing problems and device failure.
What is needed is a method and apparatus that produces shallow trench isolation structures that are planar. In addition, a method and apparatus is needed that eliminates or reduces dishing of dielectric material that results from chemical mechanical polishing of shallow trench isolation structures. The method and apparatus of the present invention provides a solution to the above needs.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus that reduces dishing of dielectric material that results from chemical mechanical polishing of shallow trench isolation structures. Also, the method and apparatus of the present invention provides for forming shallow trench isolation structures that are planar.
A method for shallow trench isolation is disclosed that forms a shallow trench isolation structure having a planar top surface. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer.
Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. In the present embodiment, the etch step is a selective etch that selectively etches polysilicon. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally.
An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Optionally, an oxidation step and a TEOS removal step can be performed. The optional oxidation step repairs damage caused by the trench etch step. The optional TEOS removal step removes the TEOS layer.
Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. In the present embodiment, silicon dioxide is used as a dielectric material and a high-density plasma deposition process is used to deposit the silicon dioxide. Because the selective etch moves the side surfaces of the polysilicon layer laterally, the deposited dielectric material extends past the edges of the trench. Thus, the dielectric material overlies the silicon nitride layer near the edges of the trench.
The substrate is then polished using a chemical mechanical polishing process. The chemical mechanical polishing step removes the polysilicon layer and forms a plug of dielectric material that fills the trench. In the present embodiment, a silica-based slurry is used. Because polysilicon has a higher removal rate as compared to silicon dioxide under normal silica-based slurry chemical mechanical polishing processes, a hump will develop within the top surface of the silicon dioxide. As the chemical mechanical polishing process progresses, the hump acts as a cushion in reducing the dishing of silicon dioxide. Thereby, the chemical mechanical polishing process produces a plug of dielectric material that has a top surface that is planar with respect to the top of the silicon nitride layer. More particularly, the top surface is only slightly recessed, if recessed at all, as a result of dishing caused by the chemical mechanical polishing process.
Because the top surface of the semiconductor substrate is planar as a result of elimination or minimization of dishing during chemical mechanical polishing, the method and apparatus of the present invention provides a superior shallow trench isolation structure as compared to prior art shallow trench isolation structures having significant dishing. Therefore, the method and apparatus of the present invention allows for formation of overlying layers and structures that are more uniform than those formed over prior art shallow trench isolation structures having significant dishing. Thus;, the present invention provides manufacturability and yield improvements as compared to prior art processes.
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Chen Feng
Goh Wang Ling
Lee Kong Hean
Lim Seng-Keong Victor
Chartered Semiconductor Manufacturing Limited
Fourson George
Wagner , Murabito & Hao LLP
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