Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-01-18
2003-04-01
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000
Reexamination Certificate
active
06541349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a process to form planarized shallow trench isolation (STI) methods and structures using a non-conformal filler of insulator, preferrably a high density plasma (HDP) oxide.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers of interconnect which are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods to form isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ the formation of an conformal oxide or insulator layer which is thereafter planarized by dry etching or chemical mechanical polish (CMP) planarizing methods to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench. Such STI regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar trench isolation regions and active semiconductor regions, the limited depth of focus typically achievable with advanced photoexposure.
Two major challenges in achieving the shallow trench isolation (STI) structure are: (1) filling the narrow trenches without voids or seams defect, and (2) planarization of trenches of diverse widths. Conventional STI processes which employ conformal low pressure chemical vapor deposition (LPCVD) TEOS deposition and complicated planarization processes with multi-step photo-resist coating, reactive ion etch (RIE) etch back and chemical mechanical polish (CMP) are expensive to implement due to the multitude of process steps required. Due to the nature of conformal deposition techniques such as LPCVD TEOS, seams are virtually always present shallow trench isolation regions due to the gradual closing of the lateral trench surfaces. The seams become a major problem as the device dimensions scale downward and the aspect ratio of the STI increases.
Others problems are those found in most insulator planarization processes which are caused by the inability to control the insulator removal rate within trenches. This phenenona is known as dishing.
An advantage of non-conformal deposition processes such as high density plasma deposition (HDP) of oxide is than deposited layers do not have the seam found in conformal deposition methods. A problem with HDP is that highly chemical reactive reagents cannot be used to chemically remove the excess oxide due to the significant thickness variations present in the deposited films.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional methods, it is, therefore, an object of the present invention to provide a method for forming STI in a simple and efficient manner. The method includes the providing of a semiconductor substrate having raised and lowered regions with substantially vertical and horizontal surfaces. The vertical surfaces may have a predetermined height. Further, the method includes depositing non-conformal filler material over the horizontal surfaces to at least a thickness slightly thicker than the predetermined height so as to provide raised and lowered regions of the filler material. Thereafter, the raised regions are selective removed without intervening process steps. The preferred method of removal is by Chemical-Mechanical-Planarization.
The filler material is preferred to be non-conformal high density plasma (HDP) oxide. Neither the raised or lower regions are required to be protected by any masking layers.
An oxide pad and a nitride pad is provided on the surface of the semiconductor substrate as is conventional for the formation of the shallow trenches into which the filler material will be formed. The raised and lowered regions are formed by masking regions of the nitride pad and etching exposed areas of the nitride pad. The oxide pad and the nitride pad are removed after the CMP of the raised filler material. By providing a CMP technology which uses hard, inflexible polishing pads, the pads are not deflected into the areas of extensive filler material and it is subsequently not removed. That is, the remaining STI filler material is not subject to dishing.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
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Arthanari Senthilkumar
Mei Shaw-Ning
Vishnesky Edward J.
Brewster William M.
Chaudhuri Olik
International Business Machines - Corporation
Sabo William D.
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