Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2006-06-13
2006-06-13
Wilczewski, M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257SE21546, C257SE21549
Reexamination Certificate
active
07061075
ABSTRACT:
A film stack for forming shallow trench isolation among transistors and other devices on a semiconductor substrate is provided, including a plurality of light absorbing layers alternating between a layer of SiON and a layer of SiO2and having a combined extinction coefficient >0.5. As reflected light interacts with the light absorbing layers, a substantial amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches may be formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.
REFERENCES:
patent: 4758305 (1988-07-01), Bonifield et al.
patent: 4971655 (1990-11-01), Stefano et al.
patent: 5066615 (1991-11-01), Brady et al.
patent: 5514499 (1996-05-01), Iwamatsu et al.
patent: 5639687 (1997-06-01), Roman et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5710073 (1998-01-01), Jeng et al.
patent: 5712185 (1998-01-01), Tsai et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5858870 (1999-01-01), Zheng et al.
patent: 5886391 (1999-03-01), Niroomand et al.
patent: 5958505 (1999-09-01), Mantl
patent: 5990002 (1999-11-01), Niroomand et al.
patent: 6004850 (1999-12-01), Lucas et al.
patent: 6037276 (2000-03-01), Lin et al.
patent: 6133613 (2000-10-01), Yao et al.
patent: 6187687 (2001-02-01), Plat et al.
patent: 6228740 (2001-05-01), Niroomand et al.
patent: 6294460 (2001-09-01), Subramanian et al.
patent: 6380087 (2002-04-01), Gupta et al.
patent: 6383874 (2002-05-01), Sun et al.
patent: 6444588 (2002-09-01), Holscher et al.
patent: 6500774 (2002-12-01), Bhakta
patent: 6514667 (2003-02-01), Angelopoulos et al.
patent: 6518206 (2003-02-01), Kumar et al.
patent: 6541164 (2003-04-01), Kumar et al.
patent: 6548417 (2003-04-01), Dao et al.
patent: 6828248 (2004-12-01), Tao et al.
patent: 6864150 (2005-03-01), Lin et al.
Babcock Carl P.
Bhakta Jayendra D.
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Wilczewski M.
LandOfFree
Shallow trench isolation using antireflection layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Shallow trench isolation using antireflection layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation using antireflection layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3706887