Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-12-05
2006-12-05
Richards, N. Drew (Department: 2815)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S294000, C438S295000, C257SE21545
Reexamination Certificate
active
07144790
ABSTRACT:
A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 Å or more, and is preferably made at a middle area. Conventionally, a gate insulating layer includes a thin area of about 100 Å or less and a thick area of about 200 Å or more. On the basis of a bottom of a trench peripheral region, a middle part of the flexure may be concave or convex. Particularly, the foregoing device can effectively be applied to a self-aligned flash memory in which a width of a trench between one active region and another is about 3 micrometers or less.
REFERENCES:
patent: 5498891 (1996-03-01), Sato
patent: 5646052 (1997-07-01), Lee
patent: 6255689 (2001-07-01), Lee
patent: 6365952 (2002-04-01), Akram
F. Chau & Associates LLC
Richards N. Drew
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