Shallow trench isolation structure with low trench parasitic...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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C257S374000, C257SE29020

Reexamination Certificate

active

07619294

ABSTRACT:
Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

REFERENCES:
patent: 6008109 (1999-12-01), Fulford et al.
patent: 6159871 (2000-12-01), Loboda et al.
patent: 6368979 (2002-04-01), Wang et al.
patent: 6541367 (2003-04-01), Mandal
patent: 6797652 (2004-09-01), Ngo et al.
Stanley Wolf and Richard N. Tauber, Silicon Processing For The VLSI Era, vol. I, Lattice Press, 1986, pp. 520-535.

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