Shallow trench isolation structure

Details Shallow trench isolation structure Shallow trench isolation structure

2005-10-25

2005-10-25

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S519000

Reexamination Certificate

active

06958521

ABSTRACT:
Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

REFERENCES:
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patent: 6096598 (2000-08-01), Furukawa et al.
patent: 02-230763 (1990-09-01), None
patent: 359001 (1999-05-01), None
patent: 395014 (2000-06-01), None
patent: 426935 (2001-03-01), None
Hong Xiao, Introduction to semiconductor manufacturing technology, Copyright 2001 by Prentice-Hall Inc., Upper Saddle River, New Jersey 07458.

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