Shallow trench isolation (STI) with trench liner of...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257SE21548, C438S424000, C438S437000

Reexamination Certificate

active

07989911

ABSTRACT:
In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low voltage transistor regions, and a third trench between the first and second trenches and between and adjacent to a high voltage transistor region and a low voltage transistor region. A thicker silicon dioxide layer lines the first trench and a first portion of the third trench adjacent to a high voltage transistor region. A thinner silicon dioxide layer lines the second trench and a second portion of the third trench adjacent to a low voltage transistor region. A silicon nitride layer is present on the thinner silicon dioxide layer and lines the second trench and the second portion of the third trench but is not present on the thicker silicon dioxide layer and does not line the first trench and the first portion of the third trench.

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patent: 6486517 (2002-11-01), Park
patent: 6613647 (2003-09-01), Kim
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patent: 2004/0212035 (2004-10-01), Yeo et al.
patent: 2005/0142775 (2005-06-01), Koh
patent: 2007/0200196 (2007-08-01), Kumar
patent: 2008/0166888 (2008-07-01), Hsu et al.

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