Shallow trench isolation (STI) with trench liner of...

Details Shallow trench isolation (STI) with trench liner of... Shallow trench isolation (STI) with trench liner of...

2011-07-26

2011-07-26

Stark, Jarrett (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S437000, C257S506000, C257SE21548

Reexamination Certificate

active

07985656

ABSTRACT:
A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness. A silicon nitride layer is deposited on the silicon dioxide layer in the first and second trenches. The silicon nitride layer is then etched from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench. The exposed silicon dioxide layer in the first trench is oxidized to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench. The first and second trenches are then filled with a dielectric material.

REFERENCES:
patent: 6613647 (2003-09-01), Kim
patent: 6656783 (2003-12-01), Park
patent: 6670689 (2003-12-01), Oh et al.
patent: 2002/0070430 (2002-06-01), Oh et al.
patent: 2007/0200196 (2007-08-01), Kumar

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