Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-04-02
2001-02-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S401000, C438S633000
Reexamination Certificate
active
06194287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of manufacture of microelectronics fabrications employing photolithographic methods. More particularly, the invention relates to a method for retaining of alignment marks upon a microelectronics substrate when filling trenches formed within the substrate.
2. Description of the Related Art
The manufacture of microelectronics fabrications is accomplished by repetitive performance of photolithographic operations of mask pattern generation and pattern formation, employing additive or subtractive processes to form the microelectronics patterned layers which make up a microelectronics fabrication. These patterned layers must be accurately aligned with a previously formed patterned layer or layers. This is accomplished by providing within each photomask pattern a series of alignment marks to permit accurate positioning of the entire pattern to previously formed patterns. This is done via alignment of photomask alignment marks with corresponding substrate alignment marks. Alignment marks within substrates are commonly simple line or space structures whose sharply defined edges or steps are the reference points for pattern to pattern alignment wherein the sharply defined edges may be sensed by methods such as laser interferometry to provide accurate location data for positioning the overlying photolithographic patterns.
In many instances, the manufacturing steps and materials employed in microelectronics fabrications may fill in, cover over or otherwise obscure the alignment marks of a particular pattern, making subsequent pattern alignment difficult. One such example occurs when filling trenches within microelectronics substrates such as semiconductor integrated circuit microelectronics substrates. Such trench fling is generally done with microelectronics layers formed over and upon the substrate. Often such trench fill layers are planarized after formation, and the underlying substrate alignment marks are obliterated. Another example is the employment of a silicon nitride layer as an etch stop layer underneath other layers which are to be removed by etching or etching combined with mechanical polishing. It is desirable to employ a silicon nitride layer as thin as practicable to aid in retaining surface planarity. However, very thin silicon nitride layers may not afford adequate protection against etch penetration and damage to underlying alignment marks protected with only the thin silicon nitride layer.
It is an important aspect of microelectronics fabrication to be able to form isolation trenches within substrates and fill them with gap filling trench fill material layers formed over the substrate, but it is equally important to be able to align patterns using registration alignment marks formed upon the substrates.
It is therefore towards the goal of filling trenches within microelectronics substrates while retaining alignment registration marks on the substrate that the present invention is generally directed.
It is in addition towards the goal of providing a method for filling isolation trenches within semiconductor substrates employed within integrated circuit microelectronics fabrications while retaining alignment registration marks on the semiconductor substrate after planarization that the present invention is more specifically directed.
Various methods have been disclosed in the art of microelectronics fabrication for filling trenches within substrates within microelectronics fabrication and/or for preserving alignment mark integrity within microelectronics substrates when forming layers over those microelectronics substrates.
For example, Nasr et al., in U.S. Pat. No. 5,346,584, disclose a method for forming planarized trench isolation regions within trenches within semiconductor integrated circuit substrates. The method employs patterned polysilicon filler blocks formed within depressions over trenches filled with a conformal silicon oxide layer, which are then annealed to fill the depressions with expanded silicon oxide masses formed from the polysilicon filler blocks. The surface is then planarized by a chemical mechanical polish (CMP) method.
Further, Jain, in U.S. Pat. 5,494,854, discloses a method for forming a planarized inter-level dielectric layer interposed between patterns of a patterned conductor layers within a microelectronics fabrication. The method employs a high density plasma chemical vapor deposition (HDP-CVD) method for planarizing at least the high aspect ratio pattern followed by deposition of a sacrificial silicon oxide layer and chemical mechanical polish (CMP) planarization.
Yet further, Cho et al., in U.S. Pat. No. 5,578,519, disclose a method for forming a planarized surface on a gap filling dielectric layer employed to fill shallow isolation trenches within a microelectronics substrate while restoring access to alignment marks on the substrate. The method employs selective subtractive etching of portions of the gap filling dielectric layer followed by planarizing the surface of the remaining gap filling dielectric layer.
Yet still further, Jang et al., in U.S. Pat. No. 5,702,977, disclose a method for forming within a trench within a substrate a trench fill layer which is subsequently chemical mechanical polish (CMP) planarized without dishing within the area of the filled trench. The method employs a deposition inhibiting initial layer formed upon the regions of the substrate which do not have trenches formed therein and a deposition enhancing layer over those regions which do have trenches formed therein. The resulting differences in topography of the trench fill dielectric overlayer aid in subsequent planarization.
Still yet further, Hsu et al., in U.S. Pat. No. 5,705,320, disclose a method for keeping alignment mark and laser identity mark areas within microelectronics substrates clear after planarization of inter-level dielectric overlayers formed over the alignment marks areas. The method realizes the object by forming clearout window areas in the frame portions of the mask reticle. Thus the necessity for additional photomask operations to maintain accessibility to the alignment marks and identity marks is obviated.
Yet still further, Yano et al., in U.S. Pat. 5,721,173, disclose a method for forming and filling shallow isolation trenches within a semiconductor microelectronics substrate. The method forms trenches by etching through a silicon nitride pattern layer on a semiconductor microelectronics substrate and fills the trenches employing a silicon oxide dielectric layer. The silicon oxide dielectric layer is then covered with an etch resistant polysilicon layer which is selectively patterned to allow subsequent etching of the silicon oxide layer away from the trench areas. The etch resistant polysilicon layer is then selectively removed to form a planarized surface. The silicon nitride pattern layer for forming isolation trenches may be replaced by a polysilicon layer in a second embodiment.
Finally, Zheng et al., in U.S. Pat. 5,728,621, disclose a method for forming shallow isolation trenches within a semiconductor microelectronics substrate. The trenches are filled employing a gap filling silicon oxide dielectric trench fill layer. The trenches are separated by regions of differing widths causing the silicon oxide trench fill layer thicknesses over these differing width regions to be variable. The silicon oxide trench fill layer is then covered with a spin-on-glass (SOG) dielectric layer which minimizes the height differences in the silicon oxide layer underlying the spin-on-glass (SOG) layer. Thereafter, the substrate surface is planarized by etchback or chemical mechanical polish (CMP) planarizing methods.
Desirable within the art of microelectronics fabrication are methods for filling of trenches within substrates employed within microelectronics fabrications with trench fill layers while maintaining integrity of alignment marks formed within the substrate. Particularly desirable are methods for accomplishing this goal without additional phot
Ackerman Stephen B.
Blum David S
Bowers Charles
Saile George O.
Taiwan Semiconductor Manufacturing Company
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