Shallow trench isolation region in semiconductor device and...

Details Shallow trench isolation region in semiconductor device and... Shallow trench isolation region in semiconductor device and...

2006-12-15

2009-11-24

Dang, Trung (Department: 2892)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257SE21548

Reexamination Certificate

active

07622360

ABSTRACT:
A method of forming a device isolation region in a semiconductor device is capable of completely removing an oxide layer for trench formation in a central region of the semiconductor device without forming a moat in an edge region. The method begins with forming a sacrificial oxide and sacrificial nitride layer over a semiconductor substrate. Trenches are etched in the nitride layer, the oxide layer and the substrate in the central and edge regions, respectively. The trenches are filled with an oxide layer. The oxide layer is then polished until the sacrificial nitride layer formed in the edge region is exposed, to form a first device isolation region filling a first trench and a second device isolation region pattern filling a second trench and covering the second region. A photoresist pattern is formed over the first device isolation region and the second device isolation region pattern. The second device isolation region pattern is partially etched using the photoresist pattern as a mask to form a second device isolation region.

REFERENCES:
patent: 6838357 (2005-01-01), Chen et al.
patent: 2002/0160610 (2002-10-01), Arai et al.
patent: 2005/0269637 (2005-12-01), Iwamatsu et al.
patent: 2006/0014361 (2006-01-01), Kwon

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