Shallow trench isolation process utilizing differential liners

Details Shallow trench isolation process utilizing differential liners Shallow trench isolation process utilizing differential liners

2008-03-13

2009-12-01

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C438S218000

Reexamination Certificate

active

07626242

ABSTRACT:
A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

REFERENCES:
patent: 6482715 (2002-11-01), Park et al.
patent: 6486517 (2002-11-01), Park
patent: 6737706 (2004-05-01), Lee et al.
patent: 6770530 (2004-08-01), Efferenn et al.

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