Shallow trench isolation process for high aspect ratio trenches

Details Shallow trench isolation process for high aspect ratio trenches Shallow trench isolation process for high aspect ratio trenches

1994-04-20

1996-02-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437247, 437 63, 148DIG50, H01L 2176

Patent

active

054928583

ABSTRACT:
Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.

REFERENCES:
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4526631 (1985-07-01), Silvestri et al.
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4745081 (1988-05-01), Beyer et al.
patent: 4783238 (1988-11-01), Roesner
patent: 4876216 (1989-10-01), Tobias et al.
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5130268 (1992-07-01), Liou et al.
patent: 5173439 (1992-12-01), Dash et al.
patent: 5175122 (1992-12-01), Wang et al.
patent: 5177028 (1993-01-01), Manning
patent: 6689656 (1987-08-01), Silvestri et al.
Becker; "Low Pressure Deposition of Doped SiO.sub.2 by Pyrolysis of Tetraethylorthesilicate (TEOS)"; J. Electrochem. Soc: Solid State Science and Technology; vol. 134, No. 11, pp. 2923-2931; Nov. 1987.
T. H. Daubenspeck, J. K. DeBrosse, C. W. Koburger, M. Armocost, and J. R. Abernathey, "Planarization of ULSI Topography Over Variable Pattern Densities", J. Electrochem. Soc., vol. 138, No. 2, pp. 506-509, Feb. 1991.
B. Davari, C. W. Koburger, R. Schulz, J. D. Warnock, T. Furukawa, M. Jost Y. Taur, W. G. Schwittek, J. K. DeBrosse, M. L. Kerbaugh, and J. L. Mauer, "A New Planarization Technique, Using A Combination of RIE And Chemical Mechanical Polish (CMP)", IEDM Technical Digest, pp. 3.4.1-3.4.4, 1989.
D. J. Sheldon, C. W. Gruenshclaeger, L. Kammerdiner, N. B. Henis, P. Kelleher, and J. D. Hayden, "Application Of a Two-Layer Planarization Process To VLSI Intermetal Dielectric And Trench Isolation Processes", IEEE Transactions Semiconductor Manufacturing, 1, No. 4, 140-145, Nov. 1988.

Affiliated with

Also associated with

Rating

Shallow trench isolation process for high aspect ratio trenches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench isolation process for high aspect ratio trenches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation process for high aspect ratio trenches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1355755