Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-02-05
2000-01-04
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438692, 438784, H01L 21762
Patent
active
060109483
ABSTRACT:
A process for creating BPSG filled, shallow trench isolation regions, in a semiconductor substrate, has been developed. The process features the use of a BPSG layer with about 4 to 4.5 weight percent B.sub.2 O.sub.3, and about 4 to 4.5 weight percent P.sub.2 O.sub.5, in silicon oxide. This BPSG composition, when subjected to a high temperature anneal procedure, results in softening, or reflowing, of the BPSG layer, eliminating seams or voids, in the BPSG layer, that may have been present after BPSG deposition. The removal rate of BPSG, is lower than the removal rate of silicon oxide layer, in buffered HF solutions, thus allowing several buffered HF procedures to be performed without recessing of BPSG in the shallow trench. In addition this composition of BPSG performs as a gettering material for mobile ions, thus contributing to yield and reliability improvements, when used at the isolation region for MOSFET devices.
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Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Fourson George
Saile George O.
Taiwan Semiconductor Manufacturing Company
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