Shallow trench isolation process

Details Shallow trench isolation process Shallow trench isolation process

2002-10-15

2004-08-31

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S404000, C438S699000, C438S703000, C438S723000, C438S724000, C438S778000, C438S787000, C438S791000

Reexamination Certificate

active

06784077

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a shallow trench isolation (STI), region in a semiconductor substrate.
(2) Description of Prior Art
Insulator regions are used to provide electrical, as well as physical isolation between devices, and device regions, on a semiconductor substrate. One method of providing isolation is via formation of regions of localized oxidation of silicon (LOCOS). This procedure employs an oxidation resistant mask such as silicon nitride, to protect subsequent active device regions from LOCOS, while regions not covered by the oxidation resistant mask are subjected to the thermal oxidation procedure resulting in the formation of LOCOS or field oxide (FOX), isolation regions. However the journey to micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, have led the industry to alternative methods for forming isolation regions. The LOCOS procedure allows unwanted oxidation of semiconductor to result at the edges of the oxidation resistant, or silicon nitride masking shape, resulting in a thin silicon oxide layer, sometimes referred to “birds beak”, protruding under the oxidation resistant masks into the designed active device region. The consequence of the “birds beak” phenomena is larger than desired active device region designs, needed to accommodate the unwanted “birds beak” growth. This results in larger semiconductor chips which adversely impact device performance, as well as fabrication costs.
The use of STI technology eliminates the possibility of “birds beak” formation, and thus is extensively used with the advent of micro-miniaturization. The use of dry etched defined trenches in the semiconductor substrate, followed by insulator filling and removal of excess insulator layer, allow isolation regions to be formed, satisfying all the design demands of micro-miniaturization. To insure isolation integrity, in terms of surface states and charge, a thermally grown, silicon dioxide layer is sometimes formed as a liner layer, on the exposed surfaces of the trenches, as well as on the top sure of the semiconductor substrate, prior to filling of these same trenches with chemically vapor deposited insulator layer. However removal of a pad oxide layer from the top surface of the semiconductor substrate to expose a subsequent active device region, performed via wet etch procedures after formation of the STI regions, can result in unwanted etching of the liner layer, and of the adjacent STI region. The vulnerable regions, located at the corners of the STI regions, are exposed to the pad oxide layer, wet etch removal procedure, sometimes resulting in significant insulator removal. The removed oxide region or “ditch” can be a source for trapped contaminants, introduced during subsequent processing procedures, or the “ditch” can be a region where unwanted surface states can be initiate from.
This invention will describe a process for forming an STI region in a semiconductor substrate, featuring an additional insulator layer deposited overlying the liner layer. The additional insulator layer features a low etch rate in the solutions used to remove the pad oxide layer, thus offering protection to the oxide liner layer, and the oxide filled trenches during the pad oxide removal procedure. Prior art, such as Jang et al, in U.S. Pat. No. 6,239,002, as well Lee in U.S. Pat. No. 5,933,749, describe methods of forming STI regions in a semiconductor substrate, however those prior arts do not describe the key feature, the protective overlying insulator layer, offered in this present invention.
SUMMARY OF THE INVENTION
It is an object of this invention to form shallow trench isolation (STI), regions in top portions of a semiconductor substrate.
It is another object of this invention to form a thermally grown, silicon dioxide liner layer on the exposed surfaces of the shallow trench shapes.
It is still another object of this invention to deposit a silicon rich, silicon oxide layer, on the silicon dioxide liner layer, prior to filling the trench shapes with an insulator layer.
In accordance with the present invention a method of forming STI regions in a semiconductor substrate, featuring a silicon rich, silicon oxide layer deposited on an underlying silicon dioxide liner layer, and used to prevent removal of regions of the silicon dioxide liner layer, during subsequent wet etch procedures, is described. After definition of shallow trench shapes in a composite insulator layer comprised of an overlying silicon nitride layer, and an underlying silicon dioxide pad layer, the dry etching definition procedure is continued to form the shallow trench shapes in top portions of a semiconductor substrate. A silicon dioxide liner layer is thermally grown on the exposed semiconductor surfaces of the shallow trench shapes. A silicon rich, silicon oxide layer, is next deposited, followed by insulator filling of the shallow trench shapes. A chemical mechanical polishing (CMP) is used to remove portions of the insulator fill layer, as well as the portions of the silicon rich, silicon oxide layer, from the top surface of the silicon nitride surface, resulting in the desired STI regions. Selective removal of silicon nitride, via wet etch procedures, is followed by removal of the silicon dioxide pad oxide layer. The low etch rate of the silicon rich, silicon oxide, in the wet etchant used to remove the silicon dioxide pad layer, allowed this layer to survive, and thus protect the insulator fill layer, as well as the silicon dioxide liner layer, located in the STI regions, during this wet etch procedure.


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