Shallow trench isolation process

Details Shallow trench isolation process Shallow trench isolation process

1999-07-07

2001-02-13

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257S221000

Reexamination Certificate

active

06187649

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a process for fabricating an integrated circuit. More particularly, the present invention relates to a shallow trench isolation process.
2. Description of Related Art
Shallow trench isolation is a technique applicable for fabricating isolation devices in many different very large semiconductor integration (VLSI) circuits. Trenches are formed between the metal-oxide-semiconductor (MOS) devices over a substrate of an integration circuit. The trenches are then filled with insulation material for electrically isolating those devices.
FIGS. 1A-1F
are schematic, cross-sectional views of a conventional shallow trench isolation (STI) process.
Referring to
FIG. 1A
, a pad oxide layer
102
is grown over a substrate
100
. A silicon nitride layer
104
is formed over the pad oxide layer
102
.
Referring to
FIG. 1B
, the silicon nitride layer
104
, the pad oxide layer
102
, and the substrate
100
are patterned, and thus a trench
106
is formed in the substrate
100
. The trench
106
has a top corner
106
a.
Still referring to
FIG. 1B
, a liner oxide layer
108
is conformally formed over the trench
106
.
Referring to
FIG. 1C
, an oxide layer (not shown) is formed over the silicon nitride layer
104
and the substrate
100
, and thus the trench
106
(shown in
FIG. 1B
) is filled with the oxide layer. The oxide layer over the silicon nitride layer
104
is partially removed by chemical-mechanical polishing. Being partially removed, the remaining oxide layer is represented by reference numeral
110
.
Referring to
FIG. 1D
, the silicon nitride layer
104
(shown in
FIG. 1C
) and the pad oxide layer
102
(shown in
FIG. 1C
) are stripped by wet etching, and the oxide layer
110
thus has an exposed sidewall
110
a
. After this removing step, another wet etching step is performed to fabricate devices (not shown) over the substrate
100
. In those wet etching steps, the etching recipes used often erode the exposed sidewall
110
a
of the oxide layer
110
, and thus a hollow
112
in the oxide layer
110
is formed near the top corner
106
a
of the trench
106
. A conductive layer (not shown) is then deposited over the oxide layer
110
and the substrate
100
, but the conductive layer causes shorts through the hollow
112
between devices (not shown) subsequently formed over the substrate
100
. Moreover, the top corner
106
a
of the trench
106
, exposed when the hollow
112
is formed, greatly affects the devices over the substrate
100
greatly. This effect, known as the kink effect, is a process problem needs to be solved.
SUMMARY OF THE INVENTION
The invention provides a shallow trench isolation process. In this process, an oxide layer in a trench is formed, wherein the oxide layer fills the trench and has a sidewall above the trench. The process further comprises forming a polysilicon spacer on the sidewall and oxidizing the polysilicon spacer to transform it into an oxide spacer.
The polysilicon spacer can be formed by depositing a polysilicon layer over the oxide layer and the substrate, and then etching back the polysilicon layer to construct the polysilicon spacer. After the polysilicon spacer is formed on the sidewall of the oxide layer, a thin oxide layer is preferably formed by oxidizing surfaces of the substrate, the oxide layer, and the polysilicon spacer. The thin oxide layer is used as a sacrificial oxide layer in an ion-implantation step. After this implantation step, the thin oxide layer is removed. A thermal oxidation step is preferably performed to oxidize the polysilicon spacer and to grow a gate oxide layer over the substrate. A polysilicon layer and a tungsten silicon layer serving as a word line are sequentially formed over the gate oxide layer.
In one embodiment, the oxide layer and the trench of the substrate are fabricated as follows. A pad oxide layer and a mask pattern are sequentially formed over the substrate. The mask pattern is used as an etching mask for etching the pad oxide layer and the substrate, and thus the desired trench is formed in the substrate. A liner oxide layer is conformally grown along a surface of the trench. The oxide layer filling the trench has a surface level higher than that of the silicon nitride layer. The oxide layer over the silicon nitride layer is removed. The silicon nitride layer is removed over the substrate, thereby the oxide layer has an exposed sidewall.
The polysilicon spacer or the oxide spacer protects the sidewall of the oxide layer from being eroded in subsequent etching steps. Therefore, the oxide layer has a smooth sidewall without any hollow therein in this present invention, unlike the oxide layer formed in a conventional STI process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4599789 (1986-07-01), Gasner
patent: 5733383 (1998-03-01), Fazan et al.
patent: 5960298 (1999-09-01), Kim
patent: 6022781 (2000-02-01), Noble, Jr. et al.

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