Shallow trench isolation process

Details Shallow trench isolation process Shallow trench isolation process

1999-11-15

2001-03-06

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S694000, C438S697000, C438S699000, C438S700000

Reexamination Certificate

active

06197691

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming shallow trench isolation structures in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is now commonly used in the art as an alternative to local oxidation of silicon (LOCOS) for forming isolations between active device areas in the integrated circuit. STI offers the advantages of smaller isolation area and better surface planarization when compared to LOCOS.
FIG. 1
illustrates an integrated circuit device of the prior art. A semiconductor substrate
10
is shown. A polish stop layer
14
is formed overlying the semiconductor substrate
10
. The polish stop layer
14
is typically comprised of silicon nitride. Trenches for shallow trench isolations have been etched through the polish stop layer
14
and into the semiconductor substrate
10
.
Referring now to
FIG. 2
, a gap fill layer
18
is deposited overlying the polish stop layer and filling the trenches. The gap fill layer
18
is comprised of a non-conductive dielectric material. In this example, a high density plasma oxide (HDP oxide) is deposited. In a HDP oxide deposition, the process simultaneously deposits and etches the oxide material. Using this oxide results in the very good fill characteristics, such as no voids in the oxide in the trenches. In addition, the HDP oxide deposits to near 45 degree angle topologies at trench corners. In the art, the gap fill layer
18
would be deposited to a depth that will allow it to exceed the height of the etch stop layer
14
that borders the trenches by a safe amount L
1
.
Referring now to
FIG. 3
, a photoresist layer
22
is deposited overlying the gap fill layer
18
. A photolithographic step is required here because it is desirable to remove the excess gap fill layer
18
in the areas outside of the trenches (that is, the active areas). The photoresist layer
18
is exposed (typically as an oversized reverse mask of the trenches) and developed to form the protective mask shown.
Referring now to
FIG. 4
, excess gap fill layer
18
is etched down. The photoresist layer
22
is stripped away following the etch.
Referring now to
FIG. 5
, the gap fill layer
18
is polished down to the top surface of the etch stop layer
14
to complete the STI structures.
There are three problems with the prior art technique. First, a photolithographic step is required. This mask step adds processing cost. Second, the gap fill layer
18
is over polished over the trenches. It is necessary to polish all of the oxide off the etch stop layer
14
. To insure a complete polish, some over polishing always occurs. In the prior art case, because of the over polish, dishing
26
occurs. This dishing occurs primarily over wide trench areas and can cause excessive device leakage in some cases. Third, the final thickness L
2
of the gap fill layer
18
is difficult to control. The way the process is constructed, the thickness will depend on a complex function of deposited gap fill layer
18
thickness, etch stop layer
14
thickness, the amount of etch down of the gap fill layer
18
, and variation in the polishing down process.
Several prior art approaches disclose methods to form and planarize shallow trench isolations. U.S. Pat. No. 5,665,202 to Subramanian et al discloses an STI process. Trenches are formed with silicon nitride etch stops bordering. Silicon dioxide is deposited to fill the trenches above the top of the silicon nitride etch stops. A second silicon nitride layer is deposited overlying the silicon dioxide fill layer. A first polish down is performed to exposed the silicon dioxide layer. In one embodiment, a second polish down is performed to remove the exposed silicon dioxide layer down to the top surface of the first silicon nitride etch stop. In a second embodiment, the second polish down removes the silicon dioxide only down to near the top of the first silicon nitride layer. Variation in pad pressure is used to control selectivity in the chemical mechanical polish (CMP) operation. U.S. Pat. No. 5,817,567 to Jang et al teaches a STI process. After an oxide fill of the trench, a silicon nitride layer is deposited overlying the oxide layer. A CMP is performed to remove the silicon nitride and the oxide in peak areas and to planarize the topology. A single etch is used to remove both the remaining silicon nitride and a portion of the oxide. A second CMP is used to polish down the oxide to the top surface of the trench edges. U.S. Pat. No. 5,173,439 to Dash et al teaches another STI process. A polysilicon layer is deposited overlying the oxide fill layer. A CMP is performed to remove a portion of the polysilicon layer, leaving the layer overlying the oxide over the trenches. An anisotropic etch is performed to etch down the oxide layer where not covered by the polysilicon. A second CMP is performed to polish down the remaining polysilicon and the oxide layer to the top of the trench. U.S. Pat. No. 5,880,007 to Varian et al discloses another process to form STI. An HDP oxide is deposited to completely fill the trenches. A polysilicon layer is deposited overlying the oxide layer. The polysilicon is deposited so that the top surface of the polysilicon overlying the trenches is higher than the top surface of the oxide layer over the non-trench (higher) areas. A CMP is performed to expose the oxide. The exposed oxide is etched down. The polysilicon is etched away. A second CMP is performed to polish down the oxide to the top of the trenches. U.S. Pat. No. 5,792,707 to Chung teaches a process to planarize interlevel dielectrics. A photolithography step is used to define areas where the interlevel oxide will be protected from etching and polishing. U.S. Pat. No. 5,498,565 to Gocho et al discloses several STI processes.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate shallow trench isolations where no masking step is required in the planarization sequence.
Another further object of the present invention is to provide a method to fabricate shallow trench isolations where oxide dishing is eliminated.
Yet another further object of the present invention is to provide a method to fabricate shallow trench isolations where the final thickness of the trench oxide is better controlled.
In accordance with the objects of this invention, a new method of forming shallow trench isolations has been achieved. A semiconductor substrate is provided. A first etch stop layer is deposited overlying the semiconductor substrate. The first etch stop layer and the semiconductor substrate are etched to form trenches for planned shallow trench isolations. A gap fill layer of high density plasma oxide is deposited overlying the first etch stop layer and filling the trenches. The deposition of the gap fill layer is stopped before the planar top surface of the gap fill layer overlying the trenches reaches the level of the top surface of the first etch stop layer bordering the trenches. The gap fill layer is etched so that the gap fill layer overlying the trenches does not contact the gap fill layer overlying the first etch stop layer. A second etch stop layer is deposited overlying the gap fill layer and the first etch stop layer. The deposition of the second etch stop layer is stopped before the planar top surface of the second etch stop layer overlying the trenches reaches the level of the top surface of the first etch stop layer. The second etch stop layer is polished down to selectively expose the gap fill layer in areas not overlying the trenches. The exposed gap fill layer is etched away. The second etch stop layer and the first etch stop layer are etched away, and the integrated circuit device is completed.


REFERENCES:
patent: 5173439 (1992-

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