Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-11-23
2001-01-16
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000, C438S429000, C438S430000, C438S433000
Reexamination Certificate
active
06174786
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
Not Applicable
FIELD OF THE INVENTION
This invention relates to the manufacturing of semiconductor devices. More specifically, the invention relates to providing an improved shallow trench isolation process.
BACKGROUND OF THE INVENTION
It is well known that adjacent devices, such as transistors, in metal oxide semiconductor (MOS) circuits need to be isolated. Several isolation techniques have been developed to accomplish this isolation and include localized oxidation isolation (LOCOS), poly buffered LOCOS, and shallow trench isolation. Although LOCOS is a commonly used technique, shallow trench isolation provides an improved ability to reduce the distance between transistors necessary to isolate the transistors. Therefore, shallow trench isolation advantageously allows for a greater density of transistors in a given area. During shallow trench isolation, trenches separating the transistors are formed into the silicon substrate and typically vary in depth between 0.3M and 0.8M. These trenches can be formed by many methods, but the trenches are commonly provided by anisotropically etching the substrate using dry etching. However, a problem associated with the method of shallow trench isolation is that the top corners of the trench provided by this method typically are sharp and have little rounding. A problem with sharp top trench corner having little rounding is that the corner provides an abrupt transition from the transistor active area to isolation. If a polysilicon gate wraps around into the isolation corner, a parasitic conduction path can occur in the sub-threshold regime. This causes the well-known and undesired “double hump” in the drain current to drain voltage (I-V) curve. One method of producing rounded top corners is by high temperature field oxidation. In this manner, the corner is rounded by growing a thin thermal oxide layer in the trench. However, the degree of rounding of the corners is difficult to control using this process.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an improved shallow trench isolation method that provides rounding of top corners.
It is still another object of the invention is to provide an improved shallow trench isolation method that provides top corner rounding without the need of high temperature field oxidation.
These and other objects of the invention are achieved by the subject method which includes the steps of forming an oxide layer; forming a mask layer; anisotropically etching the mask layer; forming a second oxide layer; forming a spacer; forming rounded end caps adjacent the mask; and transferring the rounding of the caps to the top corners of the trench.
The oxide layer is formed over a substrate of the semiconductor device, and the mask layer is then formed over the oxide layer. The mask layer is anisotropically etched to form the mask and an opening in the mask. The opening in the mask exposes the substrate with the width of the opening preferably being greater than the width of the trench.
Blanket etching the spacer forms the rounded end caps. The rounded end caps are adjacent to the mask on opposite ends of the opening, and the distance between the end caps is about equal to the width of the trench. The trench is formed by plasma etching the trench. During this process, the rounding of the end caps is transferred to the top corners of a trench.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are described below.
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Fritzinger Larry B.
Kelley Patrick J.
Lee Cynthia C.
Molloy John Simon
Singh Ranbir
Lucent Technologies - Inc.
Pham Long
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