Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-08-25
2001-02-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000
Reexamination Certificate
active
06191001
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for isolating devices built on a semiconductor substrate. More particularly, the present invention relates to a shallow trench isolation method.
BACKGROUND OF THE INVENTION
As methods of fabricating semiconductor integrated circuits (IC) continually improve, the number of devices that may be introduced into a single semiconductor chip has increased, while the size of each device has decreased. Millions of devices may now be fabricated on a single chip. Particularly in such high-density semiconductor devices, individual devices must be properly isolated in order to maintain acceptable performance. For example, improper isolation between transistors may cause additional leakage current, resulting in poor noise margin, threshold voltage shift, cross-talk and circuit latchup.
In metal-oxide semiconductor (MOS) technology, isolation is generally achieved by forming isolation regions between neighboring active areas. Typically, an isolation area is formed by ion-doping a channel stop of polarity opposite to the source electrode and the drain electrode of the IC device, and growing a thick oxide, often referred to as field oxide (FOX). The channel stop and the FOX cause the threshold voltage in the isolation area to be much higher than those in the neighboring active regions, thereby insuring that surface inversion does not occur under the FOX area.
One method known in the art for laterally isolating IC devices is known as Local Oxidation of Silicon (LOCOS). A LOCOS structure is typically formed by using a patterned silicon nitride layer together with a pad oxide to mask the active areas, followed by ion-implantation in the isolation region. Thereafter, a thick field oxide is grown locally in the isolation region. The LOCOS structure possesses some inherent drawbacks, such as lateral oxidation of the silicon underneath the silicon nitride mask, which makes the edge of the field oxide region resemble the shape of a bird's beak. The bird's beak shape causes unacceptably large encroachment of the field oxide into the device active regions.
Shallow trench isolation (STI) technology was created to overcome the disadvantages of the LOCOS technique. A basic STI procedure involves etching shallow trenches into the silicon substrate, depositing a field oxide onto the substrate, and planarizing the deposited oxide layer using chemical-mechanical polishing (CMP).
While the conventional STI process prevents the bird's beak effect and reduces cross-disturbance between adjacent electric fields, it is difficult to evenly planarize the deposited field oxide layer. As the field oxide layer is deposited, peaks and bumps in the field oxide layer are created due to the uneven topography of the semiconductor device. The peaks and bumps, which are primarily located above active areas of the device, make it difficult to evenly planarize the field oxide layer using conventional techniques, such as chemical-mechanical polishing. An unevenly planarized surface may result in inadequate isolation, resulting in poor electrical characteristics. Additionally, an unevenly planarized wafer makes subsequent processing steps, such as photolithography, difficult to perform.
One method known in the art for dealing with this problem involves creating a reverse tone structure, wherein a photo-resist layer is patterned on the exposed surface of the deposited field oxide layer to mask the trench areas. Thereafter, the peaks and bumps formed over the active areas of the device are etched such that they have a substantially planar top surface. Thus, after removal of the photo-resist layer, a relatively uniform surface is created for planarization. However, over-etching is possible, resulting in damage to the field oxide isolation region or active area.
To avoid the problem of over-etching, another solution to the planarization problem involves use of “dummy” features in the trench isolation area. Using this method, instead of creating a uniform trench across the isolation region, a plurality of dummy active areas is defined within the isolation region. The plurality of protruding dummy active areas within the trench creates multiple bumps or peaks when the field oxide layer is deposited. Although the use of dummy features within the field oxide region diminishes the difficulty of planarization, the presence of larger, “true” active areas, and corresponding wider peaks of deposited field oxide, can still cause problems during planarization. Additionally, the photomask used to define the dummy active areas within the field oxide regions is expensive to prepare due to the large number of dummy features that is typically required.
Thus, there remains a need in the art for a method of achieving even planarization during a shallow trench isolation procedure.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing a semiconductor device using shallow trench isolation that allows even planarization of the field oxide or dielectric layer. The method of the present invention includes forming a plurality of protrusions in the exposed surface of the mask layer overlying the active areas of the device. By forming a plurality of protrusions in this area of the mask layer, the subsequent deposition of the dielectric layer creates a plurality of small peaks or bumps in the portion of the dielectric layer overlying the active areas of the device. The small peaks or bumps are easily planarized using conventional techniques, such as chemical-mechanical polishing, without the need for dummy features in the trench area of the device.
In one embodiment, the method of the present invention includes forming a pad oxide layer on a semiconductor substrate and forming a mask layer on the exposed surface of the pad oxide layer. An active area and an isolation area are defined on the substrate and a trench is formed in the defined isolation area, the trench extending through the mask layer and pad oxide layer and into the substrate. A plurality of protrusions in the exposed surface of the mask layer overlying the defined active area are formed. Thereafter, a dielectric layer is deposited on the exposed surface of the mask layer and in the trench. Planarization of the dielectric layer may then be performed.
Preferably, the plurality of protrusions described above are formed by using photolithography and etching techniques known in the art. For example, a photo-resist layer may be formed on the exposed surface of the mask layer and in the trench. The photo-resist layer is patterned such that the photo-resist layer defines a plurality of protrusion areas and a depression area within the defined active area of the device. A portion of the mask layer in the defined depression area is removed to form a plurality of protrusions in the mask layer. Thereafter, the remaining portion of the photo-resist layer may be removed.
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Chen Alan Sangone
Choi Seungmoo
Cwynar Donald Thomas
Doyle Timothy Edward
Giniecki Troy A.
Lucent Technologies - Inc.
Nelms David
Vu David
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