Shallow trench isolation having an etching stop layer and...

Details Shallow trench isolation having an etching stop layer and... Shallow trench isolation having an etching stop layer and...

2000-10-25

2002-06-11

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S723000, C438S724000

Reexamination Certificate

active

06403483

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a shallow trench isolation (STI) and its method of fabrication, and more particularly to a shallow trench isolation (STI) having an etching stop layer and its method of fabrication.
2. Description of the Prior Art
Referring to FIG.
1
through
FIG. 9
, the cross-sectional side views of a conventional method for fabricating a shallow trench are depicted in sequence.
Referring now to
FIG. 1
, a cross-sectional view of the starting step is schematically shown. In
FIG. 1
, the stacked structure
11
, consisting of a silicon oxide layer
12
, a polysilicon layer
14
and a silicon nitride layer
16
, is formed on the surface of the substrate
10
.
Next, as shown in
FIG. 2
, a resist layer
20
is formed on the surface of the silicon nitride layer
16
by photolithographic technique. Then, using the resist layer
20
as a mask, the stacked structure
11
and the substrate
10
are sequentially etched to form a shallow trench
22
.
Now as shown in
FIG. 3
, the resist layer
20
is removed. Afterward, a thin oxide
30
is formed, by thermal oxidation, on the bottom and side walls of the shallow trench
22
.
Referring now to
FIG. 4
, the silicon oxide layer
40
is formed over the substrate
100
, so as to fill the shallow trench
22
Now as shown in
FIG. 5
, a portion of the silicon oxide layer
40
is removed, usually by chemical mechanical polishing (CMP) and then etching, to leave the silicon oxide layer
40
a
(e.g. Conventional isolation), within the shallow trench
22
, whose upper surface is higher than the upper surface of the polysilicon layer
14
.
Referring to
FIG. 6
, the silicon nitride layer
16
is removed. The polysilicon layer
60
and the silicide layer
62
are formed overlaying the substrate
10
.
Next, referring to
FIG. 7
, the silicide
62
, the polysilicon layer
60
, and the polysilicon layer
14
are etched by using anisotropic etching to form polycide gates
71
and
73
.
Then, as shown in
FIG. 8
, an oxide layer
81
is formed to serve as a passivation. Afterward, using photolithographic technique, the resist pattern
80
is formed to expose a portion surface of the oxide layer
81
.
Next, referring to
FIG. 9
, using the resist pattern
80
as a mask, a portion of oxide layer
81
is etched, by conventional dry etching, to form a contact hole
85
. Because of the occurrence of a misalignment, silicon oxide layer
40
a
(e.g. Conventional isolation) would be etched into a gap
86
. A conductive material is filled in the contact hole
85
and the gap
86
, thereby forming a conductive plug
91
and an interconnection
90
.
As a result of the misalignment in the photolithographic process, the silicon oxide
40
a
will be etched into a gap within the substrate. Moreover, the conductive material in the gap will result in a substrate leakage.
SUMMARY OF THE INVENTION
In view of the above disadvantage, an object of the invention is to provide a method for fabricating a shallow trench isolation having an etching stop layer, thereby preventing the gap within the shallow trench isolation.
The above object is attained by providing a method for fabricating a shallow trench isolation having an etching stop layer, comprising the steps of: (a) providing a substrate; (b) forming a stacked structure consisting of a first insulated layer, a conductive layer, and a first shield layer in sequence, on said substrate; (c) defining said stacked structure and said substrate so as to form a shallow trench; (d) forming a second insulated layer over said substrate, to fill said shallow trench; (e) etching said second insulated layer so as to leave a portion of said second insulated layer remaining in said shallow trench, and to form a concave portion in the top position of said shallow trench; (f) removing said first shield layer; (g) forming a second shield layer over said substrate, to fill said concave portion; and (h) etching said second shield layer so as to leave a portion of said second shield layer in the concave portion, to serve as an etching stop layer.
Furthermore, the above object is attained by providing a method for fabricating a shallow trench isolation having an etching stop layer, comprising the steps of: (a) providing a silicon substrate; (b) forming a stacked structure consisting of a first silicon oxide layer, a polysilicon layer, and a first silicon nitride layer in sequence on said silicon substrate; (c) defining said stacked structure and said silicon substrate so as to form a shallow trench; (d) forming a second silicon oxide layer over said substrate, to fill said shallow trench using a high density plasma deposition; (e) polishing said second silicon oxide layer so as to leave a portion of said second silicon oxide layer remaining in said shallow trench, and to form a concave portion in the top position of said shallow trench, by chemical mechanical polishing; (f) removing said first silicon nitride layer; (g) forming a second silicon nitride layer over said silicon substrate, to fill said concave portion; and (h) polishing said second silicon nitride layer so as to leave a portion of said second silicon nitride layer in the concave portion, to serve as an etching stop layer.


REFERENCES:
patent: 5929504 (1999-07-01), Mogami et al.
patent: 5943590 (1999-08-01), Wang et al.
patent: 6197691 (2001-03-01), Lee
patent: 6225225 (2001-05-01), Goh et al.
patent: 6287939 (2001-09-01), Huang et al.

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