Shallow trench isolation formation without planarization mask

Details Shallow trench isolation formation without planarization mask Shallow trench isolation formation without planarization mask

1999-08-11

2002-01-29

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06342432

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high-density semiconductor devices with submicron design features and active regions isolated by shallow insulated trenches.
BACKGROUND ART
Current demands for high density and performance associated with ultra large-scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically doped monocrystalline silicon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then filled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a nitride polish stop layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then filled with an insulating material (or “trench fill”), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized to provide a flat surface at the trench edges, as by chemical-mechanical polishing (CMP) to the nitride polish stop, and the nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
Disadvantageously, during planarization, an excess amount of the trench fill tends to be removed, resulting in the top of the trench fill being “dished” in the middle; i.e., lower than the top of the trench. This condition complicates subsequent processing, thereby lowering manufacturing yield and increasing production costs.
To prevent dishing, conventional STI formation methodologies include the formation of an additional photolithographic mask, known as a planarization mask. As shown in
FIG. 1A
, a trench
100
a
is formed in a semiconductor substrate
100
after deposition of a pad oxide layer
105
and a nitride polish stop layer
110
. An oxide liner
115
is then thermally grown, and trench
100
a
is filled with an insulating material
120
. Insulating material
120
is then polished, as by CMP, to obtain a flat upper surface, as shown in FIG.
1
B. The portion of insulating material
120
above trench
100
a
is masked by photoresist mask
125
(see FIG.
1
C), then the portions of insulating material
120
unprotected by mask
125
are etched, as shown in FIG.
1
D. Mask
125
is then removed, and insulating material
120
is further polished, as by CMP, down to the level of polish stop layer
110
(see FIG.
1
E). After polish stop
110
is removed, the trench fill
120
is above the top of trench
100
a
, as shown in FIG.
1
F.
Although this conventional methodology avoids dishing of the trench fill, it requires the formation of a complex photolithographic planarization mask, which significantly increases production costs and reduces manufacturing throughput.
There exists a need for a method of manufacturing a semiconductor device with STI wherein the trench fill is not dished and the STI formation process does not require the formation of an expensive planarization mask.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having STI without dishing of the insulating material filling the trench and without forming a planarization mask.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming a first polish stop layer on a main surface of a semiconductor substrate or an epitaxial layer formed on the semiconductor substrate; forming a trench in the substrate or epitaxial layer; depositing a first insulating layer to fill the trench and cover the first polish stop layer such that a trough is formed in the first insulating layer above the trench; forming a second polish stop layer on the first insulating layer; depositing a second insulating layer to fill the trough and cover the second polish stop layer; polishing the second insulating layer to expose a portion of the second polish stop layer above the first polish stop layer; etching to remove the exposed portion of the second polish stop layer; and polishing to expose the first polish stop layer and a portion of the second polish stop layer above the trench.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 4876217 (1989-10-01), Zdebel
patent: 5923993 (1999-07-01), Sahota
patent: 6001708 (1999-12-01), Liu et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6087262 (2000-07-01), Yang et al.
Wolf et al. “Silicon Processing for the VLSI Era” Lattice Press, 1986, vol. 1, p. 194.

Affiliated with

Also associated with

Rating

Shallow trench isolation formation without planarization mask does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench isolation formation without planarization mask, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation formation without planarization mask will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2852112