Shallow trench isolation formation with sidewall spacer

Details Shallow trench isolation formation with sidewall spacer Shallow trench isolation formation with sidewall spacer

1999-09-13

2001-06-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S221000, C257S510000

Reexamination Certificate

active

06251749

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods and in particular to isolation structures such as shallow trench isolation.
Background: Device Isolation
Electric circuits are implemented by connecting isolated devices through specific conducting paths. Therefore, to fabricate electric circuits from monolithic bodies of silicon, devices must be created in the substrate and isolated from one another. These devices are only later interconnected to form the desired circuit. Isolation of devices in the substrate of an integrated circuit is also important for other reasons. For example, the state (On or Off) and conductance of individual insulated gate field effect transistors (MOSFETs) can only be controlled if proper isolation exists among devices. If not, leakage currents may occur, causing dc power dissipation, noise-margin degradation, and voltage shift on dynamic nodes. In CMOS circuits, leakage current in the isolation region can also escalate latchup. Therefore, device isolation technology is critically important.
Background: Shallow Trench Isolation
One method for isolating devices from each other is shallow trench isolation (STI). In the standard STI process the pad
510
is oxidized from the silicon substrate
520
and a dummy nitride layer
530
is deposited as shown in FIG.
5
(
a
). Next, a moat pattern photoresist layer
540
is deposited as shown in FIG.
5
(
b
). Then a relatively shallow trench
550
0.3-0.5 microns) is etched into the silicon substrate
520
between devices as shown in FIG.
5
(
c
). A short thermal liner oxidation
560
is grown on the trench
550
walls as shown in FIG.
5
(
d
) to control the Si—SiO
2
interface quality. The shallow trench
550
is then refilled by depositing an oxide
570
or other insulating material as shown in FIG.
5
(
e
). Next, the surface is planarized by chemical mechanical polishing (CMP) as shown in FIG.
5
(
f
) and then the dummy nitride
530
is stripped away as shown in FIG.
5
(
g
). Finally, an acid deglaze is performed resulting in the completed STI
501
structure as shown in FIG.
5
(
h
). It should be noted that there is an STI shoulder
561
, i.e., the STI is not perfectly planarized with the silicon substrate.
Background: Metal Gate
In recent CMOS technology, a metal gate has been introduced to significantly reduce the gate resistance. One example of a metal gate is a stack structure of tungsten (W), titanium nitride (TiN), and polysilicon. If a self-aligned-contact process is employed, the stack structure becomes even more complex because silicon nitride (SiN) may be used for caps or sidewalls on a metallization layer. An example of the more complicated structure has layers of silicon nitride (SiN), W, TiN, and polysilicon.
Etching such a stack is not trivial. Typically the process and etchant is changed for each layer depending on which layer is being etched. If the over-etching is too short, filaments
301
remain at the shoulders of STI
320
in the areas where the tungsten
310
is vertically the thickest as shown in FIG.
3
. However, if the over-etching is too long, pits
401
are formed which penetrate the titanium nitride
410
, polysilicon
420
, gate oxide
430
and reach into the silicon substrate
440
as shown in FIG.
4
. This also is undesirable. Thus, it is apparent that the process margin for metal gate etching is very narrow, especially in the tungsten etching step.
One solution to this problem is simply to reduce the step height of the STI shoulder
561
. However, the problem with this solution is that stringent control of the gap-filling oxide deposition and CMP steps is needed because the total height of the STI defines the step height.
Background: Moat Corner Shape
Another problem with the prior art STIs is the shape of the moat corner. In STI processes, the silicon substrate is oxidized (typically liner oxidation) after the shallow silicon trench is etched. The shoulder of the moats are so sharp that the oxidation does not proceed uniformly, thus creating two problems.
One of the problems is current leakage. MOS transistors with thinner gate oxide have lower threshold voltages. If the moat corner touches the polysilicon of the metal gate stack, that portion has a lower threshold voltage leading to undesired current leakage between the source and the drain of the transistor.
Another problem created by the sharp moat corner is the reliability of the gate oxide. If the moat corner touches the polysilicon of the metal gate stack, the thinner gate oxide in the moat corner may break down.
Background: Contact Etching
In the prior art, there was a problem with penetration into the STI after a contact etch. The problem will be illustrated with reference to FIG.
6
. In the prior art, the STI
610
was configured as depicted in FIG.
6
(
a
) with liner oxide
620
and without sidewalls. A silicon nitride layer
630
was deposited to achieve a self-aligned contact etch, followed by deposition of a silicon oxide layer
640
and a photoresist layer
650
as depicted in FIG.
6
(
b
). During the contact etch, the structure appeared as depicted in FIG.
6
(
c
). Because of misalignment of contact pattern photoresist layer
650
to moat
660
and nitride thinning on the STI
610
shoulder, the contact etching would sometimes penetrate
670
deeply into the STI
610
as depicted in FIG.
6
(
d
).
Innovative Structures and Methods
The present application discloses a shallow trench isolation (STI) with sidewalls as well as a process for fabricating such a structure.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following: By inserting sidewalls into the STI process, the slopes of the shoulders of the STI are smoothed. Therefore, the topography on which the metal gate stack is deposited becomes smoother and the vertical thickness of the tungsten (W) in the shoulder is reduced. Thus, the process margin of the metal gate etching, especially the W etching step, becomes wider. Furthermore, the moat corner of the present disclosure does not touch the polysilicon because of the presence of the sidewall. Therefore, the current leak of the transfer gate and the gate oxide reliability in the moat corner are not concerns. An additional advantage of the method and structure of the present disclosure is the tolerance to misalignment of the contact patterning to moat. Using the method of the prior art, a misaligned contact could penetrate into the STI. This is a serious issue, particularly when the thin silicon nitride layer is used for the self-aligned contact process. The thin nitride layer is used to stop the self-aligned contact etching. However, the layer tends to be thinner in the moat shoulder and, therefore, can lead to penetration into the STI. When the methods and structures of the present disclosure are employed, the topography of the moat shoulder is more relaxed. Therefore, the nitride layer for the self-aligned contact is not thinned. Thus, penetration into the STI does not occur regardless of whether there is misalignment of the contact pattern relative to the moat.


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