Shallow trench isolation fill process

Details Shallow trench isolation fill process Shallow trench isolation fill process

2002-06-18

2003-12-30

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S050000, C257S499000, C257S514000, C438S410000, C438S424000, C438S445000

Reexamination Certificate

active

06670691

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particularly to a method for filling narrow isolation trenches having high-aspect ratios.
BACKGROUND OF THE INVENTION
Transistor memory arrays are typically fabricated on a silicon wafer. The process usually begins by depositing a layer of pad oxide on the wafer substrate. A nitride mask is then deposited over the pad oxide and etched to define active regions on the silicon substrate. An isolation technology is then used to create isolation regions between the active regions to electrically isolate the active regions from one another. In shallow trench isolation (STI) for example, shallow trenches are etched into the silicon substrate in the openings in the nitride mask between the active regions. A liner oxidation process is then performed in the trenches in which a layer of thermal oxide is grown. Next, an isolation dielectric such as TEOS (tetraethyl orthosilicate) or HDP (high-density plasma) is deposited over the silicon substrate and is then polished back so that it remains only in the trenches, its top surface level with the nitride mask. After the isolation dielectric is polished back the nitride mask is stripped and layers of polysilicon are then patterned to define stacked gate structures for the semiconductor device.
Unfortunately, as device sizes become increasingly smaller, e.g., sub-half micron, the trenches in core array are scaled down in width to increase device densities while trenches in circuitry that handle high voltages are still relatively wider in width. One problem with the narrow trenches having high-aspect ratios is that it is more difficult to fill the trenches with oxide that is void-free. The consistency of void-free gap fill has a significant effect on the subsequent integration process steps and on final device yield and performance.
FIG. 1A
is a top view of a silicon wafer
10
after isolation dielectric deposition, and two cross-sectional views of the wafer
10
. The dotted lines in the top view are graphical representations of trench isolation areas
12
beneath the layer of isolation dielectric
14
, which is shown in the cross-sectional views deposited over the nitride mask
16
to fill the trenches
12
. Trench
12
a
is a narrow trench and trench
12
b
is one having a wider width. Conventional isolation dielectrics
14
, such as oxide, are limited in that their capabilities are dependent upon the aspect ratios of the trenches. Therefore, when high-aspect ratio narrow trenches
12
a
are filled with conventional isolation dielectrics
14
, defects
18
such as voids commonly form in the isolation dielectric
14
. Such defects
18
in the oxide can significantly affect final device yield and performance.
Accordingly what is needed is a method for filling narrow trench isolation structures with an isolation material without the formation of voids in the insulating material. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention is directed to semiconductor devices that include both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. The present invention provides a method for filling the high-aspect ratio isolation trenches, which pose limitations to conventional isolation dielectrics in terms of gap-fill during a semiconductor fabrication process. After isolation trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.
According to the method disclosed herein, the thick liner oxidation fills the high-aspect ratio narrow isolation trenches that cannot be adequately filled with a conventional isolation dielectric.


REFERENCES:
patent: 5130268 (1992-07-01), Liou et al.
patent: 5410176 (1995-04-01), Liou et al.
patent: 5646063 (1997-07-01), Mehta et al.
patent: 5702977 (1997-12-01), Jang et al.
patent: 2003/0030121 (2003-02-01), Heo et al.
patent: 2003/0098492 (2003-05-01), Singh et al.

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