Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-07-09
2002-11-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000, C438S693000, C438S697000, C438S710000, C438S436000, C438S396000
Reexamination Certificate
active
06475875
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form shallow trench isolation (STI), regions in a semiconductor substrate.
(2) Description of Prior Art
Insulator filled, shallow trenches, are being used in the semiconductor industry to isolate specific elements of an integrated circuit, such as transistors, diodes, capacitors, and resistors. With the advent of micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, the insulator filled, shallow trench shapes have to be formed with various widths to adequately isolate various size elements, however all shallow trench shapes have to be formed to the same depth in the semiconductor substrate, and independent of width have to be uniformly filled with an insulator layer. Due to the topography created by the various elements of the integrated circuit, and due to the varying spaces between the shallow trenches, uniform fill of all shallow trenches, independent of width, is critical, therefore insulator overfilling of all shallow trench shapes is used to guarantee complete filing of all size shallow trench shapes. The insulator overfilling procedures however result in difficulties in planarizing, or removing unwanted insulator from regions outside the shallow trenches, in regards to larger amounts of insulator formed between densely packed elements, compared to lesser amounts of insulator layer located in regions in which large spaces between shallow trenches exist. Therefore several planarization procedures, or processes used to remove unwanted insulator layer from regions outside the shallow trenches, have been developed to optimize planarization, or to obtain uniformly filled, shallow trench isolation (STI), regardless of shallow trench width, or the spacing between shallow trenches.
One such planarization procedure features the use of reverse masking, or protecting specific regions of insulator layer with a photoresist shape defined using the reverse photomask previously used to define active device regions located between shallow trench shapes. The reverse masking procedure protects against a dishing phenomena that can occur during a chemical mechanical polishing procedure, used to remove, or to planarize regions of insulator layer residing on large spaces between shallow trench shapes, or even used to protect against dishing of insulator layer residing in a wide shallow trench shape. The use of the reverse masking procedure however is costly, and complex, due to the increased photolithographic procedure.
This invention will describe a planarization procedure in which unwanted insulator layer is removed from narrow as well as from wide spaces that exist between shallow trench shapes, resulting in uniformly filled, shallow trench shapes, with the insulator fill at the same level for all shallow trench shapes, independent of the shallow trench width. The planarization procedure described in this invention is accomplished without additional, costly photolithographic procedures, realized featuring the use of a polysilicon layer used as a stop layer, with removal of the polysilicon stop layer accomplished via thermal oxidation and selective wet etch procedures. Prior art, such as Copperman et al, in U.S. Pat. No. 5,494,857, describe the use a polysilicon layer as a stop layer for STI planarization, however that prior art still involves the use of costly photolithographic procedures for planarization, in addition to removal of the polysilicon stop layer via chemical mechanical polishing procedures.
SUMMARY OF THE INVENTION
It is an object of this invention to form shallow trench isolation (STI), regions, in a semiconductor substrate, with the shallow trench regions, uniformly filled with insulator independent of shallow trench width, and independent of the space between the shallow trench shapes.
It is another object of this invention to use polysilicon as a stop layer, or to protect insulator layer in the shallow trench shapes from a dry etch procedure used to remove unwanted residual insulator layer, still remaining after a chemical mechanical polishing (CMP), planarization procedure.
It is still another object of this invention to use the polysilicon stop layer to alleviate oxide loss at STI regions during subsequent wet etch steps, via conversion to a silicon oxide layer via thermal oxidation.
In accordance with the present invention a process for forming insulator filled, shallow trench isolation (STI), regions, featuring the use of a disposable polysilicon layer used to protect the STI regions during a chemical mechanical polishing—dry etch planarization procedure, is described. After formation of various width, shallow trench shapes, in a silicon nitride layer and in a top portion of a semiconductor substrate, a first, high density plasma (HDP), procedure results in filling of all shallow trench shapes with a first insulator layer, to a level equal to the top surface of the semiconductor substrate, while thicker regions of the first insulator layer reside on the top surface of the silicon nitride shapes, located between shallow trench shapes. A thin polysilicon layer is conformally deposited, overlying the regions of first insulator layer in the shallow trench shapes, as well as overlying regions of first insulator layer residing on the silicon nitride shapes. A second HDP insulator layer then fills the spaces between silicon nitride shapes, to a level planar with the top surface of the silicon nitride shapes. A CMP procedure is next performed for planarization purposes, removing regions of second HDP insulator layer, and regions of the thin polysilicon layer, located on the top surface of the silicon nitride shapes, resulting in regions of residual second HDP insulator layer, overlying thin polysilicon layer, still located between silicon nitride shapes, and residing on the insulator filled, STI regions. The residual second HDP insulator layer is then selectively removed via dry etching procedures using the polysilicon layer as an etch stop, protecting first HDP insulator layer in the shallow trench shapes. A thermal oxidation procedure is used to convert the thin polysilicon layer to silicon oxide, followed by wet etch procedures used to remove the silicon nitride shapes, and to selectively remove the oxidized thin polysilicon layer, resulting in STI regions, comprised with shallow trench shapes of various widths, all filled with first HDP insulator layer, to a level planar with the top surface of the semiconductor substrate.
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Feng Chen
Hau Pang Chong
Hing Peter
See Alex
Anya Igwe U.
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Smith Matthew
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