Shallow trench filled with two or more dielectrics for...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S386000, C257SE21540

Reexamination Certificate

active

11339874

ABSTRACT:
A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.

REFERENCES:
patent: 4222792 (1980-09-01), Lever et al.
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4656497 (1987-04-01), Rogers et al.
patent: 4881105 (1989-11-01), Davari et al.
patent: 5081516 (1992-01-01), Haskell
patent: 5091326 (1992-02-01), Haskell
patent: 5112772 (1992-05-01), Wilson et al.
patent: 5498566 (1996-03-01), Lee
patent: 5733810 (1998-03-01), Baba et al.
patent: 5742091 (1998-04-01), Hebert
patent: 6001740 (1999-12-01), Varian et al.
patent: 6037237 (2000-03-01), Park et al.
patent: 6057207 (2000-05-01), Lin et al.
patent: 6074909 (2000-06-01), Gruening
patent: 6147394 (2000-11-01), Bruce et al.
patent: 6194283 (2001-02-01), Gardner et al.
patent: 6221734 (2001-04-01), Lin
patent: 6251747 (2001-06-01), Zheng et al.
patent: 6255176 (2001-07-01), Kim et al.
patent: 6297128 (2001-10-01), Kim et al.
patent: 6300204 (2001-10-01), Noble
patent: 6326281 (2001-12-01), Violette et al.
patent: 6380067 (2002-04-01), Subramanian et al.
patent: 6391720 (2002-05-01), Sneelal et al.
patent: 6429477 (2002-08-01), Mandelman et al.
patent: 6436833 (2002-08-01), Pang et al.
patent: 6489201 (2002-12-01), Yoon
patent: 6528386 (2003-03-01), Summerfelt et al.
patent: 6551901 (2003-04-01), Gu et al.
patent: 6624039 (2003-09-01), Abdelgadir et al.
patent: 6627946 (2003-09-01), Wang
patent: 6656783 (2003-12-01), Park
patent: 6683364 (2004-01-01), Oh et al.
patent: 6733955 (2004-05-01), Geiger et al.
patent: 6756654 (2004-06-01), Heo et al.
patent: 6828646 (2004-12-01), Marty et al.
patent: 6875649 (2005-04-01), Oh et al.
patent: 2004/0171271 (2004-09-01), Heo et al.
patent: 2004/0198019 (2004-10-01), Yasui et al.
patent: 2004/0232513 (2004-11-01), Chi et al.
patent: 2005/0221580 (2005-10-01), Saitou et al.
“Characteristics of CMOS Device Isolation for the ULSI Age” A. Byrant et al.; Int'l Eelctron Device Meetings, pp. 671-674, 1994.
“Three-Dimensional DIBL for Shallow-Trench Isolated MOSFETs” C. Wang et al.; IEEE Trans. On Electron Device, vol. 46, No. 1, pp. 139-144, 1999.
“The Impact of Isolation Pitch Scaling on Vth Flucturation in DRAM Cell Transistors due to Neighboring Drain/Source Electric Field Penetration” J.H. Sim et al.; Symposium of VLSI Technology, pp. 32-33, 1998.
“New Mechanical Reliability Issues for Deep-Submicron Devices” H. Miura et al.; Symp. Of Manuf. Tech. Workshop, Taiwan, pp. 140-147, 1998.
“High-Performance Cell Transistor Design Using Metallic Shield Embedded Shallow Trench Isolation (MSE-STI) for Gbit Generation DRAMs” J.M. Sim et al.; IEEE Trans. On Electron Devices, vol. 46, No. 6, pp. 1212-1217, 1999.
U.S. Patent Application TSMC 01-1120/1138, U.S. Appl. No. 10/268,585, filed Oct. 10, 2002.
“Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding” L.H. Huang et al.; Symposium VLSI Tech. Dig. Tech. Papers., Kyoto, Japan, pp. 57-58, 2001.
“Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFETs” K. Rim et al.; IEEE Trans. Electron Dev.; vol. 47, No. 7, pp. 1406-1415, Jul. 2000.
“Strained Si Surface Channel MOSFETs for High-Performance CMO Technology” K. Rim et al.; ISSCC, paper #73, pp. 116-117, 2001.
“Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates” M.T. Currie et al.; J. Vacuum Science Technology B., vol. 19, No. 6, pp. 2268-2279, Nov./Dec. 2001.
“Enhanced Performance in Sub-100 nm CMOSFETs Using Strained Epitaxial Silicon-Geranium” Y.C. Yeo et al.; UEDM, pp. 753-756, 2000.
“SiGe HBT Technology: A New Contender for Si-Based RF and Microwave Circuit Applications” J.D. Cressler; IEEE Trans. Microwave and Techniques, vol. 46, No. 5, pp. 572-589, 1998.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Shallow trench filled with two or more dielectrics for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench filled with two or more dielectrics for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench filled with two or more dielectrics for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3954313

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.