Shadow pipeline architecture in FIFO buffer

Details Shadow pipeline architecture in FIFO buffer Shadow pipeline architecture in FIFO buffer

1990-08-14

1994-06-28

Evans, Arthur G.

G06F 1314

Patent

active

053254872

ABSTRACT:
A FIFO buffer includes a shadow register connected at the sense amplifier output of a dual port memory. The shadow register allows data to be read from the FIFO at an increased speed since the memory delay path is eliminated by preloading data into the shadow register.
To support increased speed of the FIFO, a flag logic circuit is incorporated within the FIFO which asserts the full flag and the empty flag with minimal delay. The flag logic circuit is faster since delays due to comparison logic are eliminated.

REFERENCES:
patent: 4888739 (1989-12-01), Frederick et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 4935929 (1990-06-01), Sidman et al.
patent: 4954988 (1990-09-01), Robb
patent: 4975880 (1990-12-01), Knierim et al.
patent: 5079693 (1992-01-01), Mieler

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