Shadow memory for a SRAM and method

Details Shadow memory for a SRAM and method Shadow memory for a SRAM and method

1999-12-03

2000-10-03

Nguyen, Viet Q

Static information storage and retrieval

Powering

Conservation of power

365226, 36518502, 36518508, 365174, 365188, G11C 700

Patent

active

06128243&

ABSTRACT:
A method of operating a memory cell includes detecting a first power supply anomaly or condition. When the first power supply condition occurs, memory cell access to bit lines is disabled, a series of shadow memory access FETs within the memory cells are enabled and data from the memory cells are coupled to memory FETs within the memory cells to store data corresponding to the data from the memory cells in the memory FETs. The memory FETs include nanocrystals of semiconductor material in gate dielectrics of the FETs. Electrons are stored in the nanocrystals of semiconductor material to represent the data stored in the memory cell. When a second power supply condition is detected, the data stored in the memory FETs are written back to the memory cells.

REFERENCES:
patent: 5548550 (1996-08-01), Zanders et al.
patent: 5742557 (1998-04-01), Gibbins et al.
patent: 5896330 (1999-04-01), Gibson
patent: 6026018 (2000-02-01), Herdt et al.
patent: 6034886 (2000-03-01), Chan et al.

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