Electrical computers and digital processing systems: multicomput – Multicomputer data transferring via shared memory
Reexamination Certificate
1998-09-28
2001-09-18
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: multicomput
Multicomputer data transferring via shared memory
C711S147000, C712S031000
Reexamination Certificate
active
06292826
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to distributed memory multiprocessor architectures and, more particularly, to methods and devices for improving coding and memory referencing efficiency in distributed memory multiprocessor architectures.
Time critical data processing functions are often performed in multiprocessor architectures. Multiprocessor architectures provide superior processing speeds relative to single processor architectures by executing multiple operating system tasks concurrently. Concurrently-executing tasks, however, generally create the need to track some variables on a “per processor” basis. For example, when different processors are running different tasks concurrently, it is often necessary to simultaneously monitor which task is currently being performed by each processor. Contemporaneous monitoring has conventionally been achieved by declaring in the operating system a global variable array having the form x [NCPU−1], wherein NCPU is the number of processors supported in the multiprocessor architecture and each processor is assigned a different integer in the range zero to NCPU−1 for tracking its instance of x.
The use of global variable arrays in the form x [NCPU−1] has created complications. First, in distributed memory multiprocessor architectures, standard compilers usually assign all NCPU instances of x to contiguous addresses in a single processor's local memory. While the other processors can access their respective instances of x by referencing the remote processor's memory, the latency associated with such non-local memory referencing is often considerable. To retrieve data from a non-local memory, routing assistance of a global memory controller (GMC) shared among the processors is usually required. Such assistance typically involves resolving a global physical address (GPA) supplied by the referencing processor to the non-local memory supporting that address and routing the address accordingly. Because the GMC is a shared resource, routing assistance is often delayed while addresses previously submitted are resolved and routed. Additional time is spent routing the address once access to the GMC is secured.
A second complication arises if the multiprocessor operating system is derived from a single processor operating system. It is often the case that an operating system for a multiprocessor architecture is derived from an operating system originally designed for a single processor architecture. In that event, each single instance coded variable in the form x which will require “per processor” monitoring in the multiprocessor architecture must be recoded into the form x [NCPU−1]. Such recoding may consume considerable programming man-hours.
Accordingly, there is a need for greater localization of memory referencing in distributed memory multiprocessor architectures, particularly for variables requiring tracking on a “per processor” basis. There is also a need for a means for adapting single processor operating systems into multiprocessor operating systems without substantial recoding.
SUMMARY Of THE INVENTION
In its most basic feature, the present invention addresses the shortcomings of global variable arrays in distributed memory multiprocessor architectures through the configuration of distributed “shadow” variable arrays. An array having dimensions 1×N is declared in operating system source code for a distributed memory multiprocessor architecture. The declared array includes N single instance variables which must be known on a “per processor” basis. When an initial processor becomes active, the declared array is configured in a memory local to the initial processor. As each additional processor becomes active, a shadow array comprising the same single instance variables and format is configured in a memory local to the additional processor and made locally referenceable. A patchwork of shadow arrays is thereby established in which each processor may reference local memory to access its own value set for the N single instance variables in the array. Greater localization of memory referencing in a distributed memory multiprocessor architecture is achieved. The single instance variable format of the arrays also advantageously facilitates migration from an existing single processor operating system to a multiprocessor operating system without substantial recoding.
These and other aspects of the present invention may be better understood by reference to the following detailed description, taken in conjunction with the accompanying drawings which are briefly described below. Of course, the actual scope of the invention is defined by the appended claims.
REFERENCES:
patent: 4862350 (1989-08-01), Orr et al.
patent: 5093913 (1992-03-01), Bishop et al.
patent: 5613071 (1997-03-01), Rankin et al.
patent: 5752068 (1998-05-01), Gilbert
patent: 5828894 (1998-10-01), Wilkinson et al.
patent: 5864738 (1999-01-01), Kessler et al.
patent: 5913227 (1999-06-01), Raz et al.
patent: 5968150 (1999-10-01), Kametani
patent: 6073247 (2000-06-01), Boutet et al.
Ciavaglia Stephen
Szajner, Jr. Edward C.
Zaifman Arthur L.
Alcatel Internetworking, Inc.
Chang Jung-won
Christie Parker & Hale LLP
Maung Zarni
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