Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2004-11-10
2008-10-21
Tung, Kee M. (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S557000
Reexamination Certificate
active
07439979
ABSTRACT:
A shader having a cache memory for storing program instructions is described. The cache memory beneficially stores both current programming instructions for a fragment program being run and “look-ahead” programming instructions. The cache memory supports a scheduler that forms program commands that control programmable processing stations. The cache memory can store multiple programming instructions for a plurality of shaders. If the cache memory does not include the desired programming instructions, a miss is asserted and a scheduler (instruction processor) recovers the programming instructions to be run. Beneficially, the scheduler recovers additional programming instructions to support the look-ahead programming. The cache memory stores program instructions by cachelines, where each cacheline comprises a plurality of programming instructions. The cache memory can also store program identifiers.
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Allen Roger L.
Bestos Rui M.
Walker Chad D.
NVIDIA Corporation
Patterson & Sheridan LLP
Richer Aaron M
Tung Kee M.
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