Seu-immune latch for gate array, standard cell, and other asic a

Details Seu-immune latch for gate array, standard cell, and other asic a Seu-immune latch for gate array, standard cell, and other asic a

1992-06-26

1994-05-10

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 307311, 307451, 307585, H03K 326, H03K 3284, H03K 342, H03K 17687

Patent

active

053110706

ABSTRACT:
A single event upset immune latch circuit comprises a first latch having first and second complementary channel inverters respective input nodes and output nodes of which are cross-coupled to one another. First second pairs of (complementary channel) decoupling transistors respectively couple the output nodes of said first and second complementary channel inverters in circuit with first and second voltage supply terminals. (Cross-)coupled with the first latch is a second latch having third and fourth complementary channel inverters, respective input nodes and output nodes of which are cross-coupled to one another. Third and fourth pairs of (complementary channel) decoupling transistors respectively couple the third and fourth complementary channel inverters in circuit with the first and second voltage supply terminals. Respective input nodes of the first and second latches are mutually (cross-)coupled with the gates of the pairs of complementary channel transistors of the first and second latches, so as to bias the gates of the first and second pairs of complementary channel transistors at voltage levels complementary to the voltage levels stored by the inverters to which they are coupled.

REFERENCES:
patent: 4782467 (1988-11-01), Belt et al.
patent: 4931990 (1990-06-01), Perkin
patent: 4970407 (1990-11-01), Patchen
patent: 4988893 (1991-01-01), Bonneau et al.
patent: 5039876 (1991-08-01), Hochwald et al.
patent: 5049760 (1991-09-01), Ooms
patent: 5103116 (1992-04-01), Sivilotti et al.
patent: 5111429 (1992-05-01), Whitaker
patent: 5175605 (1992-12-01), Pavlu et al.
Diehl, S. E., "Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMS", IEEE Transactions on Nuclear Science, vol. NS-29, No. 6, Dec. 1982; pp. 2032-2039.
Hsieh and Murley, "A Field-funneling Effect on the Collection of Alpha-Particle-Generated Carriers in Silicon Devices", IEEE Electron Device Letters, vol. EDL-2, No. 4, Apr., 1981, pp. 103-105.
Hu, C., "Alpha-Particle-Induced Field and Enhanced Collection of Carriers", IEEE Electron Device Letters, vol. EDL-3, No. 2, Feb. 1982, pp. 31-34.
Diehl, Vinson, Shafer and Mnich, "Considerations for Single Event Immune VLSI Logic", IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dc. 1983, pp. 4501-4507.
Rockett, Leonard, "An SEU-Hardened CMOS Data Latch Design", IEEE Transactions of Nuclear Science, vol. 35, No. 6, Dec., 1988, pp. 1682-1687.
Peterson and Diehl, "Suggested Single Event Upset Figure of Merit", IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec., 1983, pp. 4533-4539.
Mnich, Diehl, Shafer, Koga, Kolasinski and Ochoa, "Comparison of Analytical Models and Experimental Results for Single Event Upset in CMOS SRAMs*", IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec. 1983, pp. 4620-4623.

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