Setup/hold time control circuit

Details Setup/hold time control circuit Setup/hold time control circuit

2007-12-24

2010-12-28

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S198000, C327S141000, C327S202000, C327S293000

Reexamination Certificate

active

07859319

ABSTRACT:
A setup/hold time control circuit includes a reference signal output unit that sets any one of multiple ports as a reference port and buffers a signal input through the reference port to output as a reference signal. The setup/hold time control circuit also includes a plurality of comparative signal output units that set the remaining ports as comparative ports. The comparative signal output unit synchronizes signals that are input from the comparative ports with the reference signal and outputs the signals as internal signals. The setup/hold time control circuit improves high speed operation of a semiconductor memory device by improving upon the setup/hold time difference between multiple ports.

REFERENCES:
patent: 5043596 (1991-08-01), Masuda et al.
patent: 5644547 (1997-07-01), Grishakov et al.
patent: 6466492 (2002-10-01), Ikeda
patent: 6483376 (2002-11-01), Bienvenu et al.
patent: 6630850 (2003-10-01), Eto et al.
patent: 7317362 (2008-01-01), Sakuma et al.
patent: 2003-208303 (2003-07-01), None

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