Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2007-02-09
2009-08-11
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Powering
Conservation of power
C365S229000, C365S194000, C365S051000, C365S063000, C365S156000, C365S206000, C365S230060, C365S230050
Reexamination Certificate
active
07573775
ABSTRACT:
In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.
REFERENCES:
patent: 5808956 (1998-09-01), Maruyama
patent: 6163481 (2000-12-01), Yamada et al.
patent: 7130236 (2006-10-01), Rajwani et al.
Agarwal et al. “A Noise Tolerant Cache Design to Reduce Gate and Sub-Threshold Leakage in the Nanometer Regime,” Proc. Int. Symp. Low Power Electonics and Design, Aug. 2003 pp. 18-21.
Agarwal et al., “Leakage in Nano-Scale Technologies, Mechanisms, Impact and Design Considerations,” Proc. of Design Automation Conference, 2004, pp. 6-11.
Azizi et al., “Low-Leakage Asymmetric-Cell SRAM,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 4, Aug. 2003, pp. 701-715.
Bhavnagarwala et al., “A Pico-Joule Class, 1 GHz, 32 KByte x 64b DSP SRAM with Self Reversed Bias,” Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 251-252.
Bhavnagarwala et al., “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability,” IEEE J. Solid-State Circuits, vol. 36, No. 4, Apr. 2001, pp. 658-665.
De et al., “Techniques for Leakage Power Reduction,” Design of High-Performance Microprocessor Circuit, Circuits, IEEE, 2001, Chapter 3, pp. 46-62.
Hamzaoglu et al., “Circuit-Level Techniques to Control Gate Leakage for Sub-100nm CMOS,” Proc. Int. Symp. Low Power Electronics and Design, Aug. 2002, pp. 60-63.
Hamzaoglu et al., “Dual Vt-SRAM Cells with Full-Swing Singe-Ended Bit Line Sensing for High-Performance On-Chip Cache in 0.13um Technology Generation,” Proc. Int. Symp. Low Power Electronics Design, Jul. 2000, pp. 15-19.
Kim et al., “A Forward Body-Biased Low-Leakage SRAM Cache: Device, Circuit and Architecture Considerations,” IEEE Trans. on Very Large Scale Integration (VSLI) Systems, vol. 13, No. 3 Mar. 2005, pp. 349-357.
Kim et al., “Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors,” Proc. Int. Symp. Low Power Electronics Design, Aug. 2002, pp. 251-254.
Lee et al., “Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, No. 2, Feb. 2004, pp. 155-166.
Molina et al., “Non Redundant Data Cache,” Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003, pp. 274-277.
Preston et al., “Register Files and Caches,” Design of High-Performance Microprocessor Circuits, IEEE, 2001, pp. 285-308.
Qin et al., “SRAM Leakage Suppression by Minimizing Standby Supply Voltage,” Proc. Int. Symp. on Quality Electronic Design, Mar. 2004, 6 pages.
Sultania et al., “Tradeoffs Between Gate Oxide Leakage and Delay for Dual Tox Circuits,” Proc. Design Automation Conf., 2004, pp. 761-766.
Sirisantana et al., “High Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness,” Proc. Int. Conf. on Computer Design: VLSI in Computers and Processors, 2000, pp. 227-232.
Sirvastava, A., “Simultaneous Vt Selection and Assignment for Leakage Optimization,” Proc. Int. Symp. on Low Power Electronics Design, Aug. 2003, pp. 146-151.
Taur, Y., “CMOS Scaling and Issues in Sub-0.25 um Systems,” Design of High-Performance Microprocessor Circuits, IEEE, 2001, pp. 27-45.
Togo et al., “Multiple Thickness Gate Oxide and Dual-Gate Technologies for High-Performance Logic Embedded DRAMs,” IEDM Tech. Dig., 1998, pp. 347-350.
Wei et al., “Mixed-Vth (MVT) CMOS Circuit Design Methodology for Lower Power Applications,” Proc. Design Automation Conference, 1999, pp. 430-435.
Weiss et al., “The On-Chip 3MB Subarray Based 3rd Level Cache on an Itanium Microprocessor,” Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 112-113.
Zhang et al., “SRAM Design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction,” IEEE J. Solid-State Circuits, vol. 40, No. 4, Apr. 2005, pp. 895-901.
Zhang et al., “A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 474-475.
http://www.device.eecs.berkeley.edu/˜bsim3/bsim4.html, 1 page, 1997, Printed Apr. 23, 2007.
http://synopsys.com/products/mixedsignal/hspice/hspice.html, 3 pages, Printed Apr. 23, 2007.
Amelifard Behnam
Fallah Farzan
Pedram Massoud
Baker & Botts L.L.P.
Fujitsu Limited
Tran Andrew Q
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