Setting data retention thresholds in charge-based memory

Details Setting data retention thresholds in charge-based memory Setting data retention thresholds in charge-based memory

2001-03-15

2003-11-18

Hoff, Marc S. (Department: 2837)

Data processing: measuring, calibrating, or testing

Measurement system

Statistical measurement

C365S201000

Reexamination Certificate

active

06651032

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to computer memories.
2. Description of the Related Art
Various types of semiconductor memory are used in computers, each with its own characteristics. Some types of memory are charge-based. Charge-based memories charge up a cell to a predetermined level that represents the desired logic state. For example, a logic ‘0’ could be programmed by charging up the cell to a level above 1.5 volts, while a logic ‘1’ could be represented by keeping the charge in the cell below 1.5 volts. In some types of memories, multiple states can be represented by defining multiple ranges of charge. For example, ‘11’ might be represented by 0-1.5 volts, ‘10’ by 1.6-3.0 volts, ‘01’ by 3.1-4.5 volts, and ‘00’ by greater than 4.6-6.0 volts.
Most charge-based memories are reprogrammable while in the circuit, and many retain their data for a period of time even when electrical power is removed from them. In the programming operation, each cell can be charged up to a given state. Because of the mechanism involved in charging or discharging, an erase operation is generally performed on a large number of cells at the same time. These types of memories are generically referred to as electrically erasable read only memory (EEPROM), of which flash memories are one type. With EEPROM's, an entire block of memory must generally be erased and reprogrammed whenever any of the contents of the block are to be changed.
Once a charge-based memory cell has been programmed, it is read by comparing the amount of charge in the cell with a reference threshold level. For example, if the threshold between a logic ‘0’ and a logic ‘1’ is 1.5 volts, a reference cell will be maintained at 1.5 volts. The voltage level in the cell being read is compared to the reference voltage. If it is less than that reference voltage level, it is determined to be in one state, while if above the reference voltage level, it is determined to be in another state.
Once a memory cell has been charged to a certain level, that charge can migrate away, or ‘leak’, until the remaining charge represents a different, i.e. incorrect, state. If the charge migrates until the voltage in the cell is approximately the same as the reference level, the logic state stored in the cell can be misread, resulting in a memory failure. This is especially a problem in multi-state memory cells, in which each of the states are compressed into a relatively small voltage range.
Different types of technology are able to retain data for different periods of time before failing in this manner. Flash memory can retain data for several years without any effort to renew the charge. The amount of time a memory cell will remain ‘good’, i.e., will reliably hold a charge within the desired range, depends not only on the technology used, but can also depend on the characteristics of the memory's usage. Flash memories, for example, begin to deteriorate after program/erase cycles due to a change in the rate of leakage. Other factors can also affect the rate of this leakage, such as the bias voltages used and the operating temperature. Even the size of the memory array is a consideration (a large array is statistically more likely to have a bad cell that leaks faster, and just one bad cell can be enough to cause the memory device to fail).
FIG. 1
a
shows characteristic curves for conventional flash memory cells. In
FIG. 1
a
, the charge level representing the programmed state P and the charge level representing the erased state E leak, so that over a period of time, both approach threshold reference voltage Vth. The memory device eventually fails at time T
1
, because the charge level in that cell can no longer be reliably distinguished from the threshold voltage in at least one of the states.
In
FIG. 1
b
, due to the operational factors discussed above, the erased state leaks faster than the programmed state, and the device fails at time T
2
because the erased state can no longer be distinguished from the reference voltage. Although the programmed state has a much longer lifetime remaining, the memory device is not functional if it cannot reliably distinguish both the programmed and erased states for all cells. In
FIG. 1
c
, the programmed state deteriorates much faster than the erased state, so that the part fails at time T
3
, even though the erased state might be able to operate reliably for several more years.
In conventional memories, the reference voltage Vth is determined by assuming an average usage and deterioration, such as that shown in
FIG. 1
a
. Because of this, actual usage profiles that follow the curves of
FIG. 1
b
or
1
c
result in premature failure of the memory cells, because one of the states approaches the reference voltage threshold much faster than the other state.


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Neal et al., “A 1Mb CMOS DRAM with Design-for-Test Functions”, Feb. 21, 1986, 1986 IEEE International Solid-State Circuits Conference, pp. 264-265 and 367.

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