Set-select multiplexer with an array built-in self-test feature

Details Set-select multiplexer with an array built-in self-test feature Set-select multiplexer with an array built-in self-test feature

1996-05-06

1998-04-14

Heckler, Thomas M.

395496, G16F 104

Patent

active

057404127

ABSTRACT:
A pipelined set-associative cache data READ/WRITE access circuit advancing the processing performance speeds in microprocessor memories. It provides an apparatus and method to obtain quick access to multi-way cache memory associates for both READ and WRITE operations satisfying the required increased memory access performance speeds for modern microprocessor utilizations. Special methodology is employed to minimize the number of pathways and the pathway through-time of the longest time critical path even with a provision of array built in self test (ABIST) capability.

REFERENCES:
patent: 5557768 (1996-09-01), Braceras et al.
patent: 5561782 (1996-10-01), O'Connor
patent: 5577228 (1996-11-01), Banerjee et al.
patent: 5640527 (1997-06-01), Pecone et al.
patent: 5655105 (1997-08-01), McLaury
"A 2-ns Cycle, 3.8-ns Access 512-kb CMOSECL SRAM with a Full Pipe-lined Architecture", T.I. Chappell et al, IEEE J. Solid State Circuits, vol. 26, pp. 1577-1585, 1991.

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