1995-04-27
1996-11-12
Beausoliel, Jr., Robert W.
Excavating
G01R 3128
Patent
active
055747310
ABSTRACT:
A set/reset scan flip-flop circuit normally inhibits set/reset operations in the scan mode, but allows a set/reset occurring in the last scan cycle to pass through. The circuit includes a multiplexer that receives a data signal and a scan signal. The scan signal is selected as the multiplexer output when Test Enable, which serves as the multiplexer select signal, is active. The Test Enable signal and the set/reset signal are provided as inputs to an OR gate such that, if Test Enable is active high, then the OR gate output is also high. The OR gate output is connected to the set/reset pin of a flip-flop. The multiplexer output drives the data input of the flip-flop. Therefore, assuming that the set/reset signal is active low, when in the scan mode, i.e., Test Enable is active high, the OR gate blocks the set/reset signal from the flip-flop. However, if set/rest goes active low in the last scan cycle, then the low-going Test Enable allows the set/rest to pass through. The circuit covers both synchronous and asynchronous operation. In an alternative embodiment, the clock signal that drives the above-described circuit is also provided to the OR gate to block spurious signals at the beginning of a load cycle, thereby increasing glitch immunity.
REFERENCES:
patent: 4961013 (1990-10-01), Obermeyer, Jr. et al.
patent: 5185537 (1993-02-01), Creedon et al.
patent: 5285153 (1994-02-01), Ahanin et al.
patent: 5406216 (1995-04-01), Millman et al.
IEEE, IEEE Standard Tap & Boundary-Scan Architecture, pp. 6-4.
Beausoliel, Jr. Robert W.
National Semiconductor Corporation
Vales Phillip F.
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