Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal detecting using a clock signal
Reexamination Certificate
1999-06-22
2003-07-15
Huber, Paul W. (Department: 2653)
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal detecting using a clock signal
C369S047480, C341S068000, C375S341000
Reexamination Certificate
active
06594217
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to the field of disk drive systems, and in particular, to disk drive systems and circuitry that process servo synch marks using a two-state Viterbi circuit and an even magnet length constraint.
2. Statement of the Problem
FIG. 1
is a block diagram of a conventional disk drive system
100
connected to a computer system
102
. The disk drive system
100
includes control circuitry
104
and disk device
106
. The disk device
106
stores user data
108
and servo data
110
. The servo data
110
includes servo synch marks
112
.
In operation, the computer system
102
exchanges the user data
108
with the control circuitry
104
. The control circuitry
104
exchanges the user data
108
with the disk device
106
for storage. To facilitate these data exchanges, the disk device
106
reads and transfers the servo data
110
including the servo synch marks
112
to the control circuitry
104
. The control circuitry
104
uses the servo data
110
to control the operation of the disk device
106
.
FIG. 2
depicts a block diagram of the control circuitry
104
and the disk device
106
with an overhead view of the disk device
106
. The disk device includes a disk surface
216
and a head
218
. The disk surface
216
has circular data tracks that include the user data
108
depicted by dashed lines and the servo data
110
depicted by solid lines. The servo synch marks
112
are depicted by an “X” within the servo data
110
. The control circuitry
104
includes a read channel
222
and servo control
226
. The read channel
222
includes Viterbi circuitry
224
. The servo control
226
includes the synch mark detector
228
. There are typically many more disk surfaces, heads, data tracks, and control circuits in a disk drive, but the number depicted is restricted for clarity. For example, the read channel
222
typically includes a sampling circuit, adaptive filter, detector, and decoder.
As the disk surface
216
spins, the user data
108
and the servo data
110
pass under the head
218
. The head
218
reads and transfers this data in the analog read signal
220
to the read channel
222
. The read channel
222
samples and filters the analog read signal
220
. The read channel
222
uses the Viterbi circuitry
224
to process these filtered samples to detects bits. The read channel
222
transfers the resulting bit sequence
225
to the servo control
226
.
The synch mark detector
228
detects the servo synch marks
112
by recognizing a pattern in the bit sequence
225
. The servo control
226
uses the servo synch mark to locate desired data in a data track by tracking the time since servo synch mark detection as the disk surface
216
spins. Thus, the servo control
226
locates the user data
108
and the servo data
110
based on synch mark detection. The servo control
226
provides a position control signal
229
to the disk device
106
.
The analog read signal
220
that represents the servo synch marks
112
includes noise that disrupts synch mark detection. The Viterbi circuitry
224
processes samples of the noisy read signal
220
to select the most likely series of bits for accurate servo synch mark detection by servo synch mark detector
226
. The Viterbi circuitry
224
implements a state machine that is characterized by the number of states and permissible transitions from one state to another. The Viterbi circuitry
224
uses a D=N constraint based on the number of zeros that are required between consecutive ones in the servo data
110
. A D=0 constraint indicates that consecutive ones are permitted, and a D=1 constraint indicates that one zero is required between consecutive ones.
FIG. 3
shows a conventional state machine
324
for use in the Viterbi circuitry
224
. The state machine
324
has eight states and uses EPR4 and D=0. The state machine
324
receives filtered samples of the read signal and produces the likely bit sequence as the output.
FIG. 4
shows another conventional state machine
424
for use in the Viterbi circuitry
224
. The state machine
424
has four states and uses PR4 and D=0. The state machine
424
receives read signal samples as the input and produces the likely bit string as the output.
FIG. 5
shows another conventional state machine
524
for use in the Viterbi circuitry
224
. The state machine
524
is a reduction of the state machine
424
of FIG.
4
. The state machine
524
has two halves—
524
a
and
524
b
. The read signal samples are de-interleaved so each half
524
a
,
524
b
receives every other sample of the read signal
220
. The state machine
524
provides an interleaved bit sequence as the output.
FIG. 6
depicts a block diagram of Viterbi circuitry
624
that implements the state machine
524
. The decimator circuits each receive read signal samples as the input. The decimator circuits eliminate every other sample in an alternating fashion to generate interleaved samples for the delay circuits. The delay circuits introduce a two clock cycle delay into the interleaved samples, and provide the delayed-interleaved samples to the Viterbi detectors. The Viterbi detectors each implement one of the halves
524
a
,
524
b
of the state machine
524
. The Viterbi detectors are implemented using the sliding threshold algorithm to produce the interleaved bit sequence as the output.
The sliding threshold algorithm is a well known implementation of the Viterbi algorithm for the two-state di-code signal. The state update process of the Viterbi algorithm is reduced to comparing each input sample to two dynamic, or sliding, thresholds. Depending on the results of these comparisons, the thresholds and data path memories are updated. The details of the sliding threshold algorithm and the equivalence to the di-code Viterbi algorithm are well known.
Unfortunately, system noise causes these conventional Viterbi circuits provide bit sequences with errors. Errors in the bit sequence cause a failure of servo synch mark detection. The disk drive system
100
cannot exchange user data with the computer system
102
when servo synch mark detection fails. It should be appreciated that servo synch mark detection is critical to the operation of the disk device
100
, and to the effectiveness of the computer system
102
. Thus, improved Viterbi circuitry that provides a more accurate bit string would improve servo synch mark detection with a corresponding improvement in the operation of disk drive systems and computers.
Given the enormous growth in the demand for computer data storage, there is an acute need to continually improve the performance of disk drive systems. In particular, solutions are needed to reduce problems with servo synch mark detection. These solutions will provide for faster and more accurate data exchanges between the disk drive system and the computer system.
SUMMARY OF THE SOLUTION
The invention solves the above problem by providing improved Viterbi circuitry to process samples of the read signal to generate an accurate bit sequence for servo synch mark detection. The invention improves the operation of disk drives and computers by providing faster and more accurate data exchanges.
The invention includes disk drive circuitry, systems, and methods. The disk drive system comprises control circuitry and a disk device. The disk device transfers an analog signal representing servo data and user data from a disk device to the control circuitry. The servo data includes servo synch marks. The control circuitry includes Viterbi circuitry and servo circuitry. The Viterbi circuitry interleaves and sums samples of the analog signal. The Viterbi circuitry then processes the sums using two states, an even magnet length constraint, a D=1 constraint, and a sliding threshold algorithm to generate a bit sequence. The servo circuitry processes the bit sequence to detect the servo synch marks. The control circuitry also processes the analog signal to generate a digital signal representing the user data.
REFEREN
Chu Kim-Kwok
Cirrus Logic Inc.
Duft Setter Ollila & Bornsen LLC
Huber Paul W.
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