Servo circuit, digital PLL circuit and optical disk device

Dynamic information storage or retrieval – Condition indicating – monitoring – or testing – Including radiation storage or retrieval

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369 47, G11B 700

Patent

active

059462795

ABSTRACT:
A speed error detecting portion detects a speed error which is a frequency difference between a reproduced clock signal which is reproduced from a recording medium and a reference clock signal. A first phase error detecting portion detects a phase error which is a phase difference between the reproduced clock signal and the reference clock signal. A servo signal generating portion generates a servo signal which is used for eliminating the speed error and phase error. A second phase error detecting portion detects a phase error which is a phase difference between a reproduced synchronization signal reproduced from the recording medium separately from the reproduced clock signal and a reference synchronization signal. A reference phase changing portion changes the phase of the reference clock signal based on the phase error detected by the second phase error detecting portion. A reference frequency changing portion changes the frequency of the reference clock signal based on the phase error detected by the second phase error detecting portion.

REFERENCES:
patent: 5170386 (1992-12-01), Tateishi
patent: 5521895 (1996-05-01), Miura et al.
patent: 5528574 (1996-06-01), Takeuchi et al.
patent: 5535183 (1996-07-01), Miura et al.
patent: 5694380 (1997-12-01), Shimizume et al.
patent: 5703851 (1997-12-01), Ando

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