Service clock recovery circuit

Details Service clock recovery circuit Service clock recovery circuit

1989-10-31

1991-04-09

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

3701053, 455602, H04L 702

Patent

active

050070703

ABSTRACT:
A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.

REFERENCES:
patent: 3259738 (1981-03-01), Liskou et al.
patent: 4270183 (1981-05-01), Robinson et al.
patent: 4596026 (1986-06-01), Cease et al.
patent: 4716575 (1987-12-01), Douros et al.
"Design of PLL-Based Clock Generation Circuits," D. K. Jeong et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 2, Apr. 1987.
"Phaselock Techniques," Floyd M. Gardner, pp. 8-24, John Wiley & Sons, New York 1979.

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