Series terminated ECL buffer circuit and method with an optimize

Details Series terminated ECL buffer circuit and method with an optimize Series terminated ECL buffer circuit and method with an optimize

1989-06-23

1991-07-02

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307310, 307264, 307491, 307443, H03K 19086

Patent

active

050288202

ABSTRACT:
Series terminated ECL buffer circuit and method with an opptimized, temperature compensated output voltage swing. The circuit has a pair of node points and an output transistor configured as an emitter follower, with the base of the transistor connected to one of the node points. Resistors having different values of resistance are connected between a voltage source point and respective ones of the node points, and a temperature compensation network comprising a pair of unilaterally conductive legs of opposite polarity and different resistance values is connected between the node points. A current sink is connected selectively to the node points in response to an input signal to cause current to flow selectively through the resistors and the legs of the compensation network to provide an output voltage swing which is relatively independent of temperature and is centered within a predetermined range such as that specified by the standard "ECL100K" specification.

REFERENCES:
patent: 3590274 (1971-06-01), Marley
patent: 3622799 (1971-11-01), Marley
patent: 3758791 (1973-09-01), Taniguchi et al.
patent: 4623802 (1986-11-01), Cline et al.
patent: 4686395 (1987-08-01), Sato et al.
patent: 4849659 (1989-07-01), West

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