Series terminated CMOS output driver with impedance calibration

Details Series terminated CMOS output driver with impedance calibration Series terminated CMOS output driver with impedance calibration

2003-04-22

2004-08-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S030000, C326S086000, C326S087000

Reexamination Certificate

active

06771097

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to line drivers, and more particularly, to differential line drivers with impedance that is matched to the line.
2. Description of the Related Art
In high speed signaling systems, drivers with output impedance matched to the line impedance are used. A conventional voltage mode series terminated driver can be realized using an inverter with proper sizing of the NMOS and PMOS transistors to give an output impedance equal to the line impedance, which is typically 50 ohms. A circuit implementation of such a driver
100
in its differential form is shown in FIG.
1
.
Referring to
FIG. 1
, PMOS transistors MP
1
, MP
2
and NMOS transistors MN
1
, MN
2
are sized to give a nominal output impedance of 50 ohms to drive a 50 ohm line. To avoid excessive reflections of reverse travelling waves caused by mismatched far end terminations or discontinuities requires that the output impedance of the transmit driver be closely matched to the characteristic impedance of the line, typically within 10% or better. However, the turn-on resistance of the NMOS or PMOS transistors may vary by 50% or more across process, supply voltage and temperature variations.
The driver
100
of
FIG. 1
can be improved if the output impedance is made up of the sum of the resistance of a transistor switch and a resistor R
1
as shown in FIG.
2
.
The output impedance of the driver
200
of
FIG. 2
can be made to be dominated by the resistor R
1
, especially since the variation of a resistor across process, voltage and temperature variation is usually much less than that of a transistor. However, the variation is often still in the order of 20 to 30%. Achieving adequate output impedance matching requires some form of calibration or compensation mechanism. As shown in FIG.
3
and
FIG. 4
, this can be done by digitally trimming the resistance value if the driver
100
of
FIG. 1
or the driver
200
of
FIG. 2
is replaced by a segmented driver where segments are switched in or out by control lines ctlp
0
. . . ctlpi and cltn
0
. . . ctlni to match the output impedance of the driver to the impedance of the line as closely as possible.
FIG. 3
shows a segmented driver using the driver cell structure
100
of
FIG. 1
, and
FIG. 4
shows a segmented driver using the driver cell structure
200
of FIG.
2
. Referring to
FIG. 3
each segment of the driver is enabled only if ctlpi and ctlni is asserted high. For example if ctlp
1
and ctln
1
are asserted high, then transistors MP
1
and MN
1
are enabled to invert the input signal Vip. This corresponds to reducing the output impedance, since the turn-on resistances of MP
1
and MN
1
are added in parallel with the existing driver total output impedance.
The control lines ctlp and ctln are usually driven by a feedback control circuit that compares the output impedance of a replica output driver with that of an external reference resistor. After each comparison, a finite state machine uses the control lines ctlp and ctln to turn on or off driver segments to adjust the total driver output impedance to match and track the impedance of an external reference resistor.
There are several drawbacks to the driver structure of FIG.
4
. The signal (Vip, Vin) and control (ctlp, ctln) shares the same logic path through the logic gates. The logic gates in each driver segment introduce additional delay mismatches between the PMOS and NMOS transistor inputs, since the logic required to turn off an NMOS transistor is different from that for a PMOS transistor. This has the effect of shifting signal transitions away from the desired voltage point. Even if the logic were to be made similar, the loading for the output of the logic circuits would be different, since typically PMOS transistors are larger than NMOS transistors, and this can cause additional delay variation and mismatches.
Also, during the midlevel transition of the driver input voltage Vip, both PMOS and NMOS transistors can be turned on. This causes a large transient shoot through current given by V
DD
/(Resistance of PMOS transistor+Resistance of NMOS transistor) at that instant.
A calibration circuit that can be used to calibrate the segmented driver is shown in FIG.
5
. (Note that
FIG. 5
shows the one half of the circuit required to perform impedance calibration for the segmented driver of
FIG. 4.
) The circuit in
FIG. 5
uses a replica of the PMOS side of the segmented driver (see William J. Dally and John W. Poulton, “Digital Systems Engineering” Cambridge University Press, pp. 519-521).
The principle of operation of the circuit of
FIG. 5
is as follows: an external resistor R
EXT
and a current source
501
is used to generate a voltage reference at node V
1
. A matched current source
502
sinks current from the PMOS side of a replica segmented driver. The voltage drop across the PMOS side output impedance will determine the voltage at V
2
. The state machine will then turn on each driver segment by asserting ctlp
0
to ctlpi. As each segment is turned on, the voltage at V
2
is compared to that at V
1
. When a transition is detected, this indicates that the voltage at V
1
is nearly equal to that of V
1
. The output resistance of the PMOS side is thus matched to that of the external resistor R
EXT
.
This approach also has a number of disadvantages. Two sets of the same calibration circuitry consisting of the current sources, comparator, state machine logic are needed to calibrate both the PMOS and NMOS sides of the driver. Also, two external resistors R
EXT
and extra pads are required. Furthermore, for any transistors that are connected to a pad directly or through a resistor, special layout rules for ESD (electrostatic discharge) protection are necessary. The special layout rules cause the actual transistor layout to be much larger (4× to 10×) than without the ESD rules. Referring to
FIG. 5
, transistors MP
0
. . . MPi, as well as the transistors used to create the matched current sources
501
,
502
, need to have special ESD layout. Additionally, if matched current sources
501
,
502
and a reference resistor R
EXT
with the same impedance as the output driver are used, then the reference current source needs the same amount of current as the current that flows through the 50 ohm output driver. This current is significant, and is an inefficient use of available current. Alternatively, the reference current source can be made smaller and the reference resistor larger, but this introduces greater matching and scaling errors.
A similar scheme is mentioned in T. Gabara and S. Knauer, “Digitally Adjustable Resistors in CMOS for High Performance Applications”
IEEE Journal of Solid State Circuits,
Vol. 27, No. 8, August 1992, pp. 1176-1185, which uses as the first branch an external reference resistor in series with a bottom half of a replica driver to perform calibration. Another branch consists of the other upper half of a replica driver using another replica of the calibrated bottom half as the reference resistor. This requires extra area, since it requires three half replicas that include two bottom halves and one upper half, as well as extra power in each of the two series branches.
Accordingly, what is needed is a line driver that consumes low current and whose output impedance is closely matched to that of the transmission line.
SUMMARY OF THE INVENTION
The present invention is directed to a series terminated CMOS output driver with impedance calibration that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided a differential line driver including a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a sec

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