Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-04-23
2003-02-25
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C323S316000
Reexamination Certificate
active
06525596
ABSTRACT:
DESCRIPTION OF THE PRIOR ART
A typical semiconductor device formed into ICs has internally a large number of basic functional circuits, such as amplifier circuits, comparator circuits, and/or reference voltage generator circuits, with high integration density. An example of such semiconductor device is a regulator IC comprising an internal circuit with a configuration shown in the circuit diagram of FIG.
2
.
Referring to the circuitry of
FIG. 2
, a main current path of a transistor Q
1
of PNP type is connected in series between an input terminal
1
and an output terminal
2
, and a base of the transistor Q
1
, is connected to a ground via a main current path of a transistor Q
2
of PNP type. A resistor R
13
is arranged between the base and an emitter of the transistor Q
1
and resistors R
1
and R
2
are arranged as connected in series between the output terminal
2
and a ground. There are also configured a power supply circuit
4
b
, a reference voltage generator circuit
5
, and an error amplifier circuit
6
, in which the power supply circuit
4
b
is arranged between the input terminal
1
and a power supply terminal for the reference voltage generator circuit
5
and the error amplifier circuit
6
to connect them together. One of the input terminals of the error amplifier circuit
6
is connected to an output terminal of the reference voltage generator circuit
5
, while the other input terminal of the error amplifier circuit
6
is connected to a junction point of the resistor R
1
and the resistor R
2
, and an output terminal of the error amplifier circuit
6
is connected to a base of the transistor Q
2
.
Herein, the power supply circuit
4
b
, the reference voltage generator circuit
5
and the error amplifier circuit
6
are respectively configured as described below.
An emitter of a transistor Q
41
of PNP type is connected to the input terminal
1
, and a collector thereof is connected via a resistor R
8
and a diode D
43
to a ground. A resistor R
8
is arranged between a base of the transistor Q
41
and the input terminal
1
, a main current path of a transistor Q
42
of NPN type is arranged between the base of the transistor Q
41
and a ground, and a diode D
41
is arranged between the base and the collector of the transistor Q
41
. A base of the transistor Q
42
is connected via a resistor R
4
to a control input terminal
3
, thus to configure the power supply circuit
4
b.
Further, to the collector of the transistor Q
41
, which is a component of the power supply circuit
4
b
, are connected the respective emitters of transistors Q
51
and Q
52
, each being of PNP type. Respective bases of the transistors Q
51
and Q
52
are connected with each other, and a collector and the base of the transistor Q
51
are interconnected. Each collector of the transistors Q
51
and Q
52
is respectively connected to each collector of NPN type transistor Q
53
or Q
54
. Respective bases of the transistors Q
53
and Q
54
are connected with each other, and the collector and the base of the transistor Q
54
are interconnected. An emitter of the transistor Q
53
is connected via a series circuit composed of resistors R
10
and R
11
to a ground, and an emitter of the transistor Q
54
is connected to a junction point of the resistors R
10
and R
11
. A main current path of a transistor Q
55
whose base is in connection with a junction point of the resistor R
8
and the diode D
43
of the power supply circuit
4
b
is arranged as connected in parallel with a main current path of the transistor Q
53
, thus to configure the reference voltage generator circuit
5
.
Then, each of emitters of PNP type transistors Q
61
and Q
62
is connected to the collector of the transistor Q
41
, which is a component of the power supply circuit
4
b
. Respective bases of the transistors Q
61
and Q
62
are connected with each other, and a collector and the base of the transistor Q
62
are interconnected. Each of collectors of the transistors Q
61
and Q
62
is respectively connected to each collector of NPN type transistor Q
63
or Q
64
. Respective emitters of the transistors Q
63
and Q
64
are connected with each other, and a resistor R
12
is arranged between a common junction point of the respective emitters and a ground. A base of the transistor Q
63
is connected to the collector and the base of the transistor Q
54
which is a component of the reference voltage generator circuit
5
, and a base of the transistor Q
64
is connected to a junction point of the resistors R
1
and R
2
. A junction point of the collectors of the transistors Q
61
and Q
63
is connected to the base of the transistor Q
2
, thus to configure the error amplifier circuit
6
.
In the circuitry of
FIG. 2
, which has been configured as described above, an increased level of a control signal applied to the control input terminal
3
turns on the transistors Q
42
and Q
41
. Thereby, a drive voltage from an external power source connected to the input terminal
1
is supplied via the transistor Q
41
of the power supply circuit
4
b
to each of the internal circuitries of the reference voltage generator circuit
5
and the error amplifier circuit
6
.
In the reference voltage generator circuit
5
supplied with the drive voltage, upon starting the circuit, at first the transistor Q
55
is turned on, and a current mirror circuit composed of the transistors Q
51
and Q
52
is made operative. Secondarily, another current mirror circuit composed of the transistors Q
53
and Q
54
is made operative, which has been supplied with the current from the transistors Q
51
and Q
52
, and in turn the transistor Q
55
is turned off as the transistor Q
53
is turned on. After that, the activated reference voltage generator circuit
5
would generate a reference voltage of about 1.25V, based on a band gap of the semiconductor material, at the positions of collector and the base of the transistor Q
54
.
On the other hand, in the error amplifier circuit
6
, which has been supplied with the drive voltage, at first the transistor Q
63
supplied with the reference voltage conducts, and thereby the transistors Q
2
and Q
1
conduct. As the transistor Q
1
has conducted, an electric power from the input terminal
1
is transmitted via the transistor Q
1
to the output terminal
2
, and thus an output voltage is generated on the output terminal
2
. The output voltage generated on the output terminal
2
is divided by the resistors R
1
and R
2
, which in turn is supplied to the base of the transistor Q
64
. Subsequently, the transistor Q
64
conducts to make operative the current mirror circuit composed of the transistors Q
61
and Q
62
. After that, the activated error amplifier circuit
6
would control the current flowing through the transistors Q
2
and Q
1
in response to the reference voltage supplied to the transistor Q
63
and the divided voltage supplied to the transistor Q
64
so as to regulate the magnitude of the output voltage to be constant.
In such a circuitry as shown in
FIG. 2
, the reference voltage generator circuit
5
and the error amplifier circuit
6
are connected via the transistor Q
41
in on-state and the input terminal
1
to the external power source. Owing to this configuration, if a voltage supplied from the external power source fluctuates, the reference voltage generator circuit
5
and the error amplifier circuit
6
would be subject to a direct effect of the voltage fluctuation. In addition, there has been a problem that each of the transistors Q
51
, Q
52
, Q
61
and Q
62
, each being of PNP type, arranged in the power source side of each of the circuits
5
and
6
tends to suffer from the Early effect seriously when a high voltage is applied, or that the transistors of PNP type are subject to the effects of variations in various conditions in the manufacturing processes, resulting in the characteristic value of each product to be varied widely.
Because of these reasons mentioned above, the circuitry employing the configuration of
FIG. 2
is especially subject to the effect of the voltage fluctuati
Hosono Rinya
Kiya Yukinori
Kouchi Takeyuki
Sogabe Takashi
Cunningham Terry D.
Toko Inc.
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