Series-parallel type A-D converter for realizing high speed oper

Details Series-parallel type A-D converter for realizing high speed oper Series-parallel type A-D converter for realizing high speed oper

1994-06-23

1996-07-23

Young, Brian K.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

H03M 112

Patent

active

055394060

ABSTRACT:
An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.

REFERENCES:
patent: 5327135 (1994-07-01), Hosotani et al.
"Analysis and Design of Analog Integrated Circuits", Second Edition, by Paul R. Gray and Robert G. Meyer, 1984.
"A 40 Msps 10-bit Video BiCMOS Analog to Digital Converter" Journal of Electronics, Information and Communication Engineers of Japan, C-II, vol. J7, 4-C-II, No. 2, pp. 81-91, Feb. 1991, by Yasuhiro Sugimoto et al.
"A 10-b 75-MSPS Subranging A/D Converter with Integrated Sample and Hold", IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec., 1990, by Reinhard Petschacher et al.
"A 10-bit 20-MHz Two-Step Parallel A/D Converter with Internal S/H" IEEE Journal of Solid State Circuits, vol. 24, No. 1, Feb. 1989, by Toshihiko Shimizu et al.

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