Series-parallel A-D converter

Details Series-parallel A-D converter Series-parallel A-D converter

1993-02-02

1994-07-05

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341118, H03M 114

Patent

active

053271351

ABSTRACT:
Low-order reference potentials including high-order reference potentials (VRT, VRB, VC0 to VC6) generated from a ladder resistor and potentials (V(i, j) (i=0 to 7, j=0 to 6)) are applied to potential lines, respectively, to be transmitted by various switches to analog bus lines (FR0a to FR14a) or analog bus lines (FR0b FR14b). The low-order reference potentials are applied to the analog bus lines (FR0b to FR14b) when it is judged that a sample signal potential falls in voltage zones (Z0 to Z3) as a result of comparison with the high-order reference potentials and are applied to the analog bus lines (FR0a to FR14a) when it is judged that the sample signal potential falls in voltage zones (Z4 to Z7). This provides for reduction in the number of switches connected to each analog bus line and in parasitic capacitance, so that a settling time of the low-order reference potentials is shortened. High-speed operation of a series-parallel A-D converter is achieved.

REFERENCES:
patent: 4533903 (1985-08-01), Yamada et al.
patent: 4599599 (1986-07-01), Sekino et al.
patent: 4635036 (1987-01-01), Yoshizawa
patent: 5099240 (1992-03-01), Nakatani et al.
patent: 5194866 (1993-03-01), Imaizumi et al.

Affiliated with

Also associated with

Rating

Series-parallel A-D converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Series-parallel A-D converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Series-parallel A-D converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-798825