Series logic circuit arrangement using a plurality of complement

Details Series logic circuit arrangement using a plurality of complement Series logic circuit arrangement using a plurality of complement

1974-07-30

1976-03-16

Trafton, David L.

Communications: electrical

Systems

With specific power supply

307205, 340347DD, G08B 536

Patent

active

039450007

ABSTRACT:
A series logic circuit arrangement using a plurality of complementary IGFET's and comprising a plurality of series connected logic circuits, each of the logic circuits being designed to effect a predetermined logic function with respect to input binary coded signals by using at least one P channel IGFET and one N channel IFGET. In the negative logic system, the P channel IGFET's are arranged on a semiconductor substrate according to a logic equation of minterm-type expression, and the N channel IGFET's are arranged on the substrate according to a logic equation of maxterm-type expression, and, in the positive logic system, the N channel IGFET's are provided on the substrate according to the logic equation of minterm-type expression, and the P channel IGFET's are disposed on the substrate according to the logic equation of maxterm-type expression, thereby admitting of integrating the P and N channel IGFET's on the substrate within a smallest possible area.

REFERENCES:
patent: 3541543 (1970-11-01), Crawford et al.
patent: 3717868 (1973-02-01), Crawford et al.
patent: 3760380 (1973-09-01), Hoffman et al.
patent: 3820108 (1974-06-01), Luce
patent: 3825888 (1974-07-01), Kawagoe

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