Serially buffered medium translator

Details Serially buffered medium translator Serially buffered medium translator

1997-02-14

2001-11-20

Nguyen, Chau (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C370S503000, C713S189000

Reexamination Certificate

active

06320872

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to data medium translators, in particular, local and wide area network data medium translators.
BACKGROUND OF THE INVENTION
Previously, the most widely used approach for transmitting a first format data on a second format was to use the same approach as in the network hub. However, translation via the data hub port introduces significant data delays, typically in excess of 90 serial data bits, which reduces the network performance and adds to the limitations of the physical size of the network.
Such data delay and other data translation limitations experienced by hub and other prior data translation devices are, in large part, a result of internal transfer data from the incoming media serial format to an internal parallel format for buffering or processing, and back to the serial format for retransmission. The well established building blocks used in many such systems consist of an integrated circuit, e.g. part # DP83223, which provides the necessary electrical signalling and media state, while a second subsequently connected integrated circuit, e.g. part # DP83240, recovers the clock signal from the incoming signal, decodes or descrambles the NRZ, MLT
3
or other cipher format encrypted signal and provides a plaintext data signal in a 4-bit parallel standard. The plaintext parallel data is then received by a buffer or processor provided by a variety of integrated circuits. For hub configurations, similar parallel data paths are provided.
As demonstrated by the widespread adherence to the parallel data format by integrated circuit and equipment designers, the limitations imposed on the data flow by the parallel format are generally accepted as unavoidable, and thus the performance of data translation equipment is only marginally improved.
SUMMARY OF THE INVENTION
The apparatus and method according to the present invention provide a serially buffered data translator including physical layer devices which provide the necessary media interfacing and clock recovery and a serial stream of encrypted data to a serial buffer, which provides frame synchronization with a minimal data bit delay, typically 5 bits. In one embodiment according to the present invention, the serial buffer comprises a National Semiconductor part no. DP83222 previously intended for serial descrambling prior to data conversion to parallel format and subsequent processing, but adapted according to the present invention to provide the serial bit output prior to retransmission in the alternate medium format.
Having recognized the desirability, and providing the apparatus and method to provide data translation according to the present invention, a total translated data delay time of 15 bits or less is achieved. When compared to the typical 4-bit serial-parallel-serial data systems data delay of at least 45 bits, the apparatus of the present invention provides a significant improvement.


REFERENCES:
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ICS Data Book 1996, pp. F-47 to F-48 part No. ICS1886 Data Sheet.
ICS Internet Web Page, Feb. 1997, Part No. ICS1885/1886 Applications Note.
Nat. Semi. 1994 Data Book, pp. 1-3 to 1-12, Part. No. DP83222 Data Sheet.
Nat. Semi. 1994 Data Book, pp. 1-13 to 1-21, Part No. DP83223 Data Sheet.

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